Transcript ppt - SEAS
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 21: October 29, 2010 Registers Dynamic Logic 1 Penn ESE370 Fall2010 -- DeHon Today • Clocking – Registers – Timing discipline – Dynamic Registers • Dynamic Logic 2 Penn ESE370 Fall2010 -- DeHon Register • Passhold on input latch samples value • Holdpass on output latch presents stored value to circuit Master and Slave latches 3 Penn ESE370 Fall2010 -- DeHon Register • How long from f1 fall to output? – At least part of clkoutput (tclk-q) 4 Penn ESE370 Fall2010 -- DeHon Clock Signal • Can we use a single signal for clock? 5 Penn ESE370 Fall2010 -- DeHon Clock Issues • Possible failure modes? – Flow through during transition? – Loading on clock phases – Delay in compute f1? 6 Penn ESE370 Fall2010 -- DeHon Appropriate Delay Feed thru here also Bad. • Creates non-overlap • Too much could allow flow through Penn ESE370 Fall2010 -- DeHon Text page 339 example generation non-overlapping clocks. 7 Clocking Discipline 8 Penn ESE370 Fall2010 -- DeHon Clocking Discipline • Follow discipline of combinational logic broken by registers • Compute – From state elements – Through combinational logic – To new values for state elements • As long as clock cycle long enough, – Will get correct behavior 9 Penn ESE370 Fall2010 -- DeHon Gate-Latch-Register • • • • Transistor Count? Total Transistor Width? Capacitive load on data input? Capacitive load on clock? 10 Penn ESE370 Fall2010 -- DeHon Alternate Registers 11 Penn ESE370 Fall2010 -- DeHon How does this work as a register? 12 Penn ESE370 Fall2010 -- DeHon Compare Gate-Latch-Register • • • • Transistor Count? Total Transistor Width? Load on input? Load on Clock(s)? 13 Penn ESE370 Fall2010 -- DeHon Weaknesses? 14 Penn ESE370 Fall2010 -- DeHon Weaknesses • Hold value on capacitance – Not actively driven • Easily upset by noise – Will leak away eventually • Sets lower bound on clock frequency • Cannot “gate off” clock when not in use • Not drive to rail – Less noise margin – More static leakage – PMOS not completely off Penn ESE370 Fall2010 -- DeHon 15 How Improve? 16 Penn ESE370 Fall2010 -- DeHon Transmission Gate Register 17 Penn ESE370 Fall2010 -- DeHon Level Restore 18 Penn ESE370 Fall2010 -- DeHon CCMOS 19 Penn ESE370 Fall2010 -- DeHon Make Static Maybe reduce capacitance by swapping order of feedback and phi Penn ESE370 Fall2010 -- DeHon 20 Make Static • • • • Transistors? Total width? Clock load? Input load? 21 Penn ESE370 Fall2010 -- DeHon Class Ended Here 22 Penn ESE370 Fall2010 -- DeHon Dynamic Logic Motivation • Still like to avoid driving pullup/pulldown networks – reduce capacitive load • Power, delay • Ratioed had problems with – Large device for ratioing – Slow pullup – Static power Idea • Use clock to disable pullup during evaluation Advantages • Large device – Driven by clock not data/logic – Can pullup quickly w/out putting load on logic • Single network – pulldown Domino Logic Domino • Everything charged high – After inverter all inputs low • Disabled, waiting for an enabling transition 28 Penn ESE370 Fall2010 -- DeHon Domino or4 Domino Logic • How fast can we evaluate? – R0/2 input • Compare to CMOS case? Requirements • Single transition • All inputs at 1 during precharge – Precharge to 0 so inversion makes 1 • Non-inverting gates • Fires only once Issues • Noise sensitive • Power? – Activity? Admin • Homework 5 – Changed due date to Friday, Nov. 5th • Normal lectures next week 33 Penn ESE370 Fall2010 -- DeHon Ideas • Clocked circuit discipline – Uses state holding element – Prevents • Combinational loops • Timing assumptions • (More) complex reasoning about all possible timings • Pass-gate based register efficiency • Dynamic/clocked logic – Faster than CMOS, more noise prone 34 Penn ESE370 Fall2010 -- DeHon