Transcript ppt - SEAS

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 11: October 1, 2010
Variation
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Penn ESE370 Fall2010 -- DeHon
Previously
• Understand how to model
transistor behavior
• Given that we know its parameters
– Vdd, Vth, tOX, COX, W, L, NA …
CGC
CGCS
CGCB
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But…
• We don’t know its parameters (perfectly)
1.Fabrication parameters have error range
2.Identically drawn devices differ
3.Parameters change with environment
4.Parameters change with time
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Today
• Sources of Variation
– Fabrication
– Operation
– Aging
• Coping with Variation
– Margin
– Corners
– Binning
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Fabrication
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Process Shift
•
•
•
•
Oxide thickness
Doping level
Layer alignment
Growth and Etch times/rates
• Vary machine-to-machine, day-to-day
• Impact all transistors on wafer
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Region Correlated
• Parameters change consistently across
wafer or chip based on location
• Chemical-Mechanical Polishing (CMP)
– Dishing
• Lens distortion
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Oxide Thickness
[Asenov et al. TRED 2002]
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Line Edge Roughness
• 1.2mm and
2.4mm lines
From:
http://www.microtechweb.com/2d/lw_pict.htm
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Optical Sources
• What is the wavelength of light?
• How compare to 45nm feature size?
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Phase Shift Masking
Source
http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx
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Line Edges (PSM)
Source:
http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists
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Intel 65nm SRAM (PSM)
Source:
http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif
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Statistical
Dopant
Placement
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[Bernstein et al, IBM JRD 2006]
Random Trans-to-Trans
•
•
•
•
Random dopant fluctuation
Local oxide variation
Line edge roughness
Etch and growth rates
• Transistors differ from each other in
random ways
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Source: Noel Menezes, Intel ISPD2007
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Impact
• Changes parameters
– W, L, tOX, Vth
• Change transistor behavior
IDS 

mn COX W 
2
  VGS  VT 
 L 
2

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Example: Vth
• Many physical effects impact Vth
– Doping, dimensions, roughness
• Behavior highly dependent on Vth
IDS 
IDS
2
W 
 IS  e
 L 
Penn ESE370 Fall2010 -- DeHon

mn COX W 
  VGS  VT 
 L 
2

 VGS 


nkT / q 
 VDS 

kT / q 
1  e  1 VDS 


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Vth Variability @ 65nm
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[Bernstein et al, IBM JRD 2006]
Impact Performance
• Vth  Ids  Delay (Ron * Cload)
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Impact of Vth Variation
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FPGA Logic Variation
• Altera
Cyclone-II
• 90nm
Penn ESE370 Fall2010 -- DeHon
[Wong, FPT2007]
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Operation
Temperature
Voltage
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Temperature Changes
• Different ambient environments
– January in Maine
– August in Philly
– September in LA
– Air conditioned machine room
• Self heat from activity of chip
• Quality of heat sink
IDS
W 
 IS  e
 L 
Penn ESE370 Fall2010 -- DeHon
 VGS 


nkT / q 
 VDS 

kT / q 
1  e  1 VDS 


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Voltage
• Power supply isn’t perfect
• Differs from design to design
– Board to board?
• IR-drop in distribution
• Bounce with current spikes
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Aging
Hot Carrier
NBTI
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Hot Carriers
• Trap electrons in oxide
– Also shifts Vth
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NBTI
• Negative Bias Temperature Instability
– Interface traps, Holes
• Long-term negative gate-source voltage
– Affects PFET most
• Increase Vth
• Partially recoverable?
• Temperature dependent
Penn ESE370 Fall2010 -- DeHon
[Stott, FPGA2010]
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Measured Accelerated Aging
Penn ESE370 Fall2010 -- DeHon
[Stott, FPGA2010]
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Coping with Variation
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Variation
• See a range of parameters
– L: Lmin – Lmax
– Vth: Vth,min – Vth,max
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Variation
• Margin for expected variation
• Must assume Vth can be any value in range
– Speed  assume Vth slowest value
Ion,min=Ion(Vth,max)
Probability Distribution
Id,sat (Vgs-Vth)2
VTH
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Variation
• See a range of parameters
– L: Lmin – Lmax
– Vth: Vth,min – Vth,max
• Validate design at extremes
– Work for both Vth,min and Vth,max ?
– Design for worst-case scenario
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Margining
• Also margin for
– Temperature
– Voltage
– Aging: end-of-life
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Process Corners
• Many effects independent
• Many parameters
• With N parameters,
– Look only at extreme ends (low, high)
– How many cases?
• Try to identify the {worst,best} set of
parameters
– Slow corner of design space, fast corner
• Use corners to bracket behavior
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Range of Behavior
Probability Distribution
• Still get range of performances
• Any way to exploit the fact some are faster?
Delay
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Probability Distribution
Speed Binning
Sell
Premium
Sell
Sell
nominal cheap
Discard
Delay
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Admin
• HW4 out today
• Andrew lecture on Monday
– Explain how to understand pretty pictures
on HW4
• Andre out Tuesday
• Andre back for lecture on Wednesday
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Idea
• Parameters Approximate
• Differ
– Chip-to-chip, transistor-to-transistor, over
time
• Robust design accommodates
– Tolerance and Margins
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