Transcript ppt - SEAS

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 3: September 13, 2010
Gates from Transistors
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Previously
• Simplified models for reasoning about
transistor circuits
– Zeroth-order
– First-order
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Today
• How to construct static CMOS gates
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Outline
• Circuit understanding (preclass)
• Static CMOS
– Structure
– Inverter
– Construct gate
– Inverting
– Cascading
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What gate?
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What function?
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DeMorgan’s Law
• /f = a + b
• What is f?
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What function?
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Static CMOS Gate
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Static CMOS Gate Structure
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Static CMOS Gate Structure
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Static CMOS Gate Structure
• Drives rail-to-rail
• Input load is
capacitive
• Once charge
capacitive output,
doesn’t use energy
– (first order)
• Output actively
driven
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Inverter
• Out = /in
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Inverter
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Gate Design Example
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Gate Design
• Design gate to perform: f=(/a+/b)*/c
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f=(/a+/b)*/c
• Strategy:
1. Use static CMOS
structure
2. Design PMOS
pullup for f
3. Use DeMorgan’s
Law to determine /f
4. Design NMOS
pulldown for /f
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f=(/a+/b)*/c
• PMOS Pullup for f?
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f=(/a+/b)*/c
• What is /f ?
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f=(/a+/b)*/c
• NMOS Pulldown for
/f?
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f=(/a+/b)*/c
a
c
b
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Inverting Gate
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Inverting Stage
• Each stage of Static CMOS gate is
inverting
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Why not?
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Source/Drain Clarity
• Source is:
– Most negative terminal NMOS
• source of the elecrons
– Most positive terminal PMOS
• Source of holes
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Source Drain Annotation
S
D
S
S
D
D
D
S
D
D
S
S
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Static CMOS Source/Drains
• With PMOS on top,
NMOS on bottom
– PMOS source
always at top (near
Vdd)
– NMOS source
always at bottom
(near Gnd)
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Why not buffer?
D
S
S
D
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Why not buffer?
• Output signal not
drive to rails
• One threshold
voltage away
• True any time use
PMOS/NMOS on
“wrong” side
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How do we buffer?
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How implement OR?
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Cascading Stages
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Stages
• Can always cascade “stages” to build
more complex gates
• Could simply build nor2 at circuit level
and assemble arbitrary logic by
combining – universality
– but may not be smallest/fastest/least power
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Implement: f=a*/b
• Pullup?
• Pulldown?
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f=a*/b
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Admin
• Wednesday in Detkin (RCA) Lab
– Note prelab to design gates before lab
• Office Hours:
– Townley T1-2pm in Ketterer
• (1:15pm-2pm this week)
– DeHon T4:30pm in Moore/GRW 262
• (only to 5pm this week)
• Friday back here + HW1 due (blackboard)
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Big Idea
• Systematic
construction of any
gate from transistors
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