Transcript ppt - SEAS
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 17: October 9, 2013 Performance: Gates 1 Penn ESE370 Fall2013 -- DeHon Previously: First Order Delay • R0 = Resistance of minimum size NMOS device • I0 = Ids of minimum size NMOS device • C0 = gate capacitance of minimum size NMOS device • Rdrive = R0/Wn Idrive = WI0 Cg = WC0 • Technology independent relative delay t = R0C0 = C0/I0 • Large fanout – drive in stages Penn ESE370 Fall2013 -- DeHon 2 Today • Delay in Gates • Data Dependent Delay • Large Fanin 3 Penn ESE370 Fall2013 -- DeHon Gates 4 Penn ESE370 Fall2013 -- DeHon Data Dependent Delay • Resistance depends on input values delay depends on input data t-delays assuming minsize? assume 2C0 load 5 Penn ESE370 Fall2013 -- DeHon How Size • How size to equalize worst-case rise/fall times for Rdrive=R0/2? 6 Penn ESE370 Fall2013 -- DeHon Series Transistors 7 Penn ESE370 Fall2013 -- DeHon How Size • How size for equal rise/fall for Rdrive=R0/2? 8 Penn ESE370 Fall2013 -- DeHon Input Load • Input capacitance per input in each case? 9 Penn ESE370 Fall2013 -- DeHon Observe • Ratio of Input Load Capacitance to Output Drive Strength: CILoad/Ids – Differs with gate function • Some gates give more drive per capacitive load we pay – When Ids differ at same W 10 Penn ESE370 Fall2013 -- DeHon How Size • Size equalize rise/fall times Rdrive=R0/2? 11 Penn ESE370 Fall2013 -- DeHon Increasing Fanin • What happens to input capacitance as fanin (k) increases – Keeping output drive the same • E.g. Rdrive=R0/2 • k-input nand gate has what input capacitance? 12 Penn ESE370 Fall2013 -- DeHon Fanin • Conclude: gates slow down with fanin – Less drive per input capacitance 13 Penn ESE370 Fall2013 -- DeHon Which is Fastest? • nand32 • nand4-inv-nand4-inv-nand2 • (nand2-inv)4-nand2 14 Penn ESE370 Fall2013 -- DeHon Lesson • Large gates are slow / inefficient – High capacitive load / drive strength • Small gates can be inefficient – Need many stages • Staging over moderate size gates minimizes delay • Exact size will be technology dependent 15 Penn ESE370 Fall2013 -- DeHon Delay of each implementation? 16 Penn ESE370 Fall2013 -- DeHon Take Away? 17 Penn ESE370 Fall2013 -- DeHon Ideas • First order reason in t=R0C0 units • Gates have different efficiencies – Drive strength per unit input capacitance • Without velocity saturation – Reason to prefer nand over nor • With velocity saturation (short term), – nands and nors are similar efficiency • Large fanin and fanout slow gates – Decompose into stages – …but not too much Penn ESE370 Fall2013 -- DeHon 18 Admin • HW 6 is out • Friday – Fall Break • Back on Monday 19 Penn ESE370 Fall2013 -- DeHon