Transcript ppt - SEAS

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 6: September 10, 2014
Restoration
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Penn ESE370 Fall2014 -- DeHon
Today
• How do we make sure logic is robust
– Can assemble into any (feed forward)
graph
– Can tolerate voltage drops and noise
– ….while maintaining digital abstraction
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Outline
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Two problems
Cascade failure
Restoration
Transfer Curves
Noise Margins
Non-linear
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Two Problems
1. Output not go to rail
– Stops short of Vdd or Gnd
2. Signals may be perturbed by noise
Vx = Videal ± Vnoise
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Wire Resistance
Monday: Rwire=10Ω
Penn ESE370 Fall2014 -- DeHon
R
L
A
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Wire Resistance
• 1000 mm long wire?
• 1 cm long wire?
• Length of integrated circuit chip side?
– (we often call an IC chip a “die”)
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Die Sizes
Trans.
Year
Maker
feature
mm2
Bulldozer
1.2B
2012
AMD
32nm
315
Core i7
1.4B
2012
Intel
22nm
160
GK10
Kepler
7B
2012
NVIDIA
28nm
561
Chip
source: http://en.wikipedia.org/wiki/Transistor_count
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Implications
• What does the circuit really look like for
an inverter in the middle of the chip?
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Penn ESE370 Fall2014 -- DeHon
Implications
• What does the circuit really look like for
an inverter in the middle of the chip?
Rwire
Rwire
Rrest_of_chip
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IR-Drop
Rrest_of_chip
• Since interconnect is resistive and gates
pull current off the supply interconnect
– The Vdd seen by a gate is lower than the
supply Voltage by
• Vdrop=Isupply x Rdistribute
– Two gates in different locations
• See different Rdistribute
• Therefore, see different Vdrop
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Output not go to Rail
• Due to IR drop, “rails” for two
communicating gates may not match
Rrest_of_chip
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Two Problems
1. Output not go to rail
– Is this tolerable?
2. Signals may be perturbed by noise
– Voltage seen at input to a gate may not
lower/higher than input voltage
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Noise Sources?
• What did we see in lab when zoomed in
on signal transition?
• Signal coupling
– Crosstalk
• Leakage
• Ionizing particles
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Penn ESE370 Fall2014 -- DeHon
Signals will be degraded
1. Output not go to rail
– Is this tolerable?
2. Signals may be perturbed by noise
– Voltage seen at input to a gate may not
lower/higher than input voltage
• What happens to degraded signals?
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Preclass
• All 1’s  logical output?
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Preclass
• 1.0 inputs, gate: o=1-AB  output
voltage?
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Penn ESE370 Fall2014 -- DeHon
Preclass
• 0.95 inputs, gate: o=1-AB  output
voltage?
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Degradation
• Cannot have signal degrade across
gates
• Want to be able to cascade arbitrary set
of gates
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Gate Creed
• Gates should leave the signal “better”
than they found it
– “better”  closer to the rails
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Restoration Discipline
• Define legal inputs
– Gate works if Vin “close enough” to the rail
• Restoration
– Gate produces Vout “closer to rail”
• This tolerates some drop between one gate
and next (between out and in)
• Call this our “Noise Margin”
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Noise Margin
• Voh – output high
• Vol – output low
• Vih – input high
• Vil – input low
• NMh = Voh-Vih
• NMl = Vil-Vol
Penn ESE370 Fall2014 -- DeHon
One mechanism,
addresses numerous
noise sources.
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Restoration Discipline
(getting precise)
• Define legal inputs
– Gate works if Vin “close enough” to the rail
– Vin > Vih or Vin < Vil
• Restoration
– Gate produces Vout “closer to rail”
• Vout < Vol or Vout > Voh
Note: don’t just say Vin>Vih  Vout>Voh
Penn ESE370 Fall2014 -- DeHon
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Transfer Function
What gate is this?
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Restoring Transfer Function
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Decomposing
• What is gain?
|DVout/DVin| > 1
• Where is there gain?
• Where is there
not gain?
• Dividing point?
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Restoring Transfer Function
Vil, Vih = slope -1 points
Voh =f(Vil)
Vol=f(Vih)
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Penn ESE370 Fall2014 -- DeHon
Restoring Transfer Function
Vil, Vih = slope -1 points
Voh =f(Vil)
• Closer to rail
Vol=f(Vih)
than Vil, Vih
• Not make much
difference on
Vout
• Making Vil lower
would reduce
NM = Vil-Vol
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Penn ESE370 Fall2014 -- DeHon
Controlling Value
• Consider a nor2 gate
– If want one input to control the output
– What value should the other input be?
• We call this input the non-controlling
input since it does not determine the
output
• What should the non-controlling input
value be for a nand2 gate?
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Penn ESE370 Fall2014 -- DeHon
Restoring Transfer Function
For multi-input functions,
should be worst case.
i.e.
hold non-controlling inputs
at Vil, Vih respectively.
(relate preclass exercise)
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Ideal Transfer Function
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Linear Transfer Function?
• O=Vdd-A
Noise Margin?
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Linear Transfer Function?
• Consider two in a row (buffer)
• O1=Vdd-A
• What is transfer function to buffer output O2?
• O2=(Vdd-O1) = Vdd-(Vdd-A)=A
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Penn ESE370 Fall2014 -- DeHon
Linear Transfer Function?
• For buffer: O2=A
• Consider chain of buffers
• What happens if A drops a bit between
each buffer?
Ai+1 = Ai-Δ
Conclude: Linear transfer functions
do not provide restoration.
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Non-linearity
• Need non-linearity in transfer function
• Could not have built restoring gates with
– R, L, C circuit
– Linear elements
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Transistor Non-Linearity
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Penn ESE370 Fall2014 -- DeHon
All Gates
• If we hope to assemble design from
collection of gates,
– Voltage levels must be consistent and
supported across all gates
– Must adhere to a Vil, Vih, Vol, Voh
that is valid across entire gate set
Vol MAX g.Vol 
Vil MIN g.Vil 
Voh MIN g.Voh 
Vih MAX g.Vih 
gG
gG
Penn ESE370 Fall2014 -- DeHon
gG
gG
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Big Idea
• Need robust logic
– Can assemble into any (feed forward)
graph
– Can tolerate loss and noise
– ….while maintaining digital abstraction
• Restoration and noise margins
– Every gate makes signal “better”
– Design level of noise tolerance
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Admin
• HW2 due Thursday (tomorrow)
– Noise margin problem
• Friday in Ketterer (note combo)
– Read through HW3
– Transfer library/schematics to eniac
– Be ready to run electric and spice on linux
• CETS machines
• <or> own laptop that you bring with you
• Monday back here
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