Transcript ppt - SEAS

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 12: October 3, 2011
Variation
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Penn ESE370 Fall2011 -- DeHon
Previously
• Understand how to model
transistor behavior
• Given that we know its parameters
– Vdd, Vth, tOX, COX, W, L, NA …
CGC
CGCS
CGCB
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Penn ESE370 Fall2011 -- DeHon
But…
• We don’t know its parameters (perfectly)
1.Fabrication parameters have error range
2.Identically drawn devices differ
3.Parameters change with environment
(e.g. Temperature)
4.Parameters change with time (aging)
Why I am more concerned with
robustness than precision.
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Today
• Sources of Variation
– Fabrication
– Operation
– Aging
• Coping with Variation
– Margin
– Corners
– Binning
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Fabrication
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Process Shift
•
•
•
•
Oxide thickness
Doping level
Layer alignment
Growth and Etch rates and times
– Depend on chemical concentrations
• How precisely can we control those?
• Vary machine-to-machine, day-to-day
• Impact all transistors on wafer
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Systematic Spatial
• Parameters change consistently across
wafer or chip based on location
• Chemical-Mechanical Polishing (CMP)
– Dishing
• Lens distortion
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Penn ESE370 Fall2011 -- DeHon
FPGA Systematic Variation
• 65nm
• Virtex 5
Penn ESE370 Fall2011 -- DeHon
[Tuan et al. / ISQED 2010]
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Oxide Thickness
[Asenov et al. TRED 2002]
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Line Edge Roughness
• 1.2mm and
2.4mm lines
From:
http://www.microtechweb.com/2d/lw_pict.htm
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Penn ESE370 Fall2011 -- DeHon
Optical Sources
• What is the shortest wavelength of
visible light?
• How compare to 45nm feature size?
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Penn ESE370 Fall2011 -- DeHon
Phase Shift Masking
Today’s chips use λ=193nm
Source
http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx
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Penn ESE370 Fall2011 -- DeHon
Line Edges (PSM)
Source:
http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists
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Intel 65nm SRAM (PSM)
Source:
http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif
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Statistical
Dopant
Placement
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Penn ESE370 Fall2011 -- DeHon
[Bernstein et al, IBM JRD 2006]
Random Trans-to-Trans
•
•
•
•
Random dopant fluctuation
Local oxide variation
Line edge roughness
Etch and growth rates
– Stochastic process
• Transistors differ from each other in
random ways
Penn ESE370 Fall2011 -- DeHon
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Source: Noel Menezes, Intel ISPD2007
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Penn ESE370 Fall2011 -- DeHon
Impact
• Changes parameters
– W, L, tOX, Vth
• Change transistor behavior
– W?
– L?
– tOX?
IDS 

mn COX W 
2
  VGS  VT 
 L 
2
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Penn ESE370 Fall2011 -- DeHon

Example: Vth
• Many physical effects impact Vth
– Doping, dimensions, roughness
• Behavior highly dependent on Vth
IDS 
IDS
2
W 
 IS e
 L 
Penn ESE370 Fall2011 -- DeHon

mn COX W 
  VGS  VT 
 L 
2

VGS VT 


 nkT / q 
 VDS 

kT / q 
1  e  1 VDS 


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Vth Variability @ 65nm
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Penn ESE370 Fall2011 -- DeHon
[Bernstein et al, IBM JRD 2006]
Impact of Vth Variation?
• Higher VTH?
– Not drive as strongly
– Id,sat (Vgs-VTH)2
– Performance?
IDS 

mn COX W 
2
  VGS  VT 
 L 
2

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Penn ESE534 Spring2010 -- DeHon
Impact Performance
• Vth  Ids  Delay (Ron * Cload)
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Impact of Vth Variation
Penn ESE370 Fall2011 -- DeHon
Think NMOS Vgs = Vdd
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FPGA Logic Variation
• Xilinx Virtex 5
• 65nm
• Altera
Cyclone-II
• 90nm
[Tuan et al. / ISQED 2010]
Penn ESE370 Fall2011 -- DeHon
[Wong, FPT2007]
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Impact of Vth Variation?
• Lower VTH?
– Not turn off as well  leaks more
IDS
W 
 IS e
 L 
Penn ESE534 Spring2010 -- DeHon
VGS VT 


 nkT / q 
 VDS 

kT / q 
1  e  1 VDS 


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2004
Borkar (Intel) Micro 37 (2004)
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Operation
Temperature
Voltage
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Temperature Changes
• Different ambient environments
– January in Maine
– July in Philly
– Air conditioned machine room
• Self heat from activity of chip
• Quality of heat sink (attachment thereof)
IDS
W 
 IS e
 L 
Penn ESE370 Fall2011 -- DeHon
VGS VT 


 nkT / q 
 VDS 

kT / q 
1  e  1 VDS 


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Self Heating
Borkar (Intel) Micro 37 (2004)
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Penn ESE370 Fall2011 -- DeHon
Temperature (on current?)
• High temperature
– More free thermal energy
• Easier to conduct
• Lowers Vth
– Increase rate of collision
• Lower saturation velocity
• Lower saturation voltage
• Lower peak Ids  slows down
• Another reason don’t want chips to run hot
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Penn ESE370 Fall2011 -- DeHon
Temperature (leakage?)
• High temperature Lowers Vth
IDS
W 
 IS e
 L 
Penn ESE370 Fall2011 -- DeHon
VGS VT 


 nkT / q 
 VDS 

kT / q 
1  e  1 VDS 


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Voltage
• Power supply isn’t perfect
• Differs from design to design
– Board to board?
– How precise is regulator?
• IR-drop in distribution
• Bounce with current spikes
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Aging
Hot Carrier
NBTI
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Hot Carriers
• Trap electrons in oxide
– Also shifts Vth
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Penn ESE370 Fall2011 -- DeHon
NBTI
• Negative Bias Temperature Instability
– Interface traps, Holes
• Long-term negative gate-source voltage
– Affects PFET most
• Increase Vth
• Partially recoverable?
• Temperature dependent
Penn ESE370 Fall2011 -- DeHon
[Stott, FPGA2010]
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Measured Accelerated Aging
(Cyclone III, 65nm FPGA)
Penn ESE370 Fall2011 -- DeHon
[Stott, FPGA2010]
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Coping with Variation
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Penn ESE370 Fall2011 -- DeHon
Variation
• See a range of parameters
– L: Lmin – Lmax
– Vth: Vth,min – Vth,max
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Penn ESE370 Fall2011 -- DeHon
Impact of Vth Variation
• Higher VTH
– Not drive as strongly
– Id,sat (Vgs-VTH)2
• Lower VTH
– Not turn off as well  leaks more
IDS
W 
 IS e
 L 
Penn ESE534 Spring2010 -- DeHon
VGS VT 


 nkT / q 
 VDS 

kT / q 
1  e  1 VDS 


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Variation
• Margin for expected variation
• Must assume Vth can be any value in range
– Speed  assume Vth slowest value
Ion,min=Ion(Vth,max)
Probability Distribution
Id,sat (Vgs-Vth)2
VTH
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Gaussian Distribution
From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg
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Penn ESE534 Spring2010 -- DeHon
Impact
• Given
– Vth,nom = 250mV
– Sigma 25mV
• What maximum Vth should expect to
see for a circuit of
– 100 transistors?
– 1000 transistors?
– 109 transistors?
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Penn ESE370 Fall2011 -- DeHon
Variation
• See a range of parameters
– L: Lmin – Lmax
– Vth: Vth,min – Vth,max
• Validate design at extremes
– Work for both Vth,min and Vth,max ?
– Design for worst-case scenario
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Penn ESE370 Fall2011 -- DeHon
Margining
• Also margin for
– Temperature
– Voltage
– Aging: end-of-life
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Process Corners
• Many effects independent
• Many parameters
• With N parameters,
– Look only at extreme ends (low, high)
– How many cases?
• Try to identify the {worst,best} set of
parameters
– Slow corner of design space, fast corner
• Use corners to bracket behavior
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Range of Behavior
Probability Distribution
• Still get range of performances
• Any way to exploit the fact some are faster?
Delay
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Penn ESE370 Fall2011 -- DeHon
Probability Distribution
Speed Binning
Sell
Premium
Sell
Sell
nominal cheap
Discard
Delay
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Penn ESE370 Fall2011 -- DeHon
Admin
• HW4 out
– All but question 5 should be approachable
now
• Andre out Tuesday
• Andre back for lecture on Wednesday
– Talk about layout … HW4.Q5
• First midterm W after break
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Idea
• Parameters Approximate
• Differ
– Chip-to-chip, transistor-to-transistor, over
time
• Robust design accommodates
– Tolerance and Margins
– Doesn’t depend on precise behavior
Penn ESE370 Fall2011 -- DeHon
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