Transcript ppt - SEAS
ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 22: October 31, 2011
Pass Transistor Logic
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Teaser
• What does this do?
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Previously
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Elmore Delay
• For each resistor Ri in path
– Compute CRi = sum of all C’s downstream of Ri
– Delay through Ri is Ri×CRi
Delay
R
C
j
i
p a th
path
i
j
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Day 11
Capacitance Roundup
•
•
•
•
•
CGS=CGCS+CO
CGD=CGCD+CO
CGB=CGCB
CSB=Cdiff
CDB=Cdiff
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Impact on Capacitance
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Contact/Diffusion Capacitance
• Cj – diffusion depletion
• Cjsw – sidewall capacitance
• LS – length of diffusion
Cdiff Cdiff 0W
LS
Cdiff C j LSW C jsw 2LS W
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Today
• Elmore Delay with Cdiff>0 for CMOS
• Pass Transistor Circuit?
– Output levels
– Cascading
• Series pass transistors?
• Delay
– Level Restore
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CMOS Elmore and Cdiff
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Identify Function
• What function?
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Inverter Delay
• Delay driving self?
– Elmore
– Include Cdiff=gCgate
W=1
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Identify Capacitances
• Self output
load?
• Load presented
by A input?
• Capacitance
between pd
transistors?
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Identify Capacitances
• Equivalent RC
circuit (output
stage) A=B=0?
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Total Delay
• Total delay of
circuit?
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Cascade Delay
• Delay of chain
of n of these?
(connect Y to A)
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Pass Transistor
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Area
• Compare with CMOS circuit?
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Output
• What does output look like (DC transfer)?
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Pass TR transfer
(B=1)
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CMOS Inverter Transfer
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Reasonable Input to CMOS
Inverter?
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Pass tr xor2 with inv restore
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Required to use?
• What take to use this with CMOS
circuit?
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Restore Output
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Chain Together
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Analyze Stage
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Analyze Stage
• Equivalent circuit?
• Delay?
• Compare area and timing to CMOS
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Class ended here
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Cascading Pass Transistors
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Chain without Inverters
• What if we did this?
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Extract key path
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Voltage of Chain
• What is voltage at output?
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How compare
• Compare
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DC Analysis
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DC Analysis – chain of 6
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Conclude
• Can chain any number of pass
transistors and only drop a single Vth
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Capacitance
• What is Capacitance per stage?
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Delay
• Delay as a function of chain length?
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Compare
• CMOS
• Buffered Pass TR
• Unbuffered Pass TR
• Delay
• Area
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Pass TR Tree
• What if we did this?
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Path
• What’s different about this?
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Demonstration Circuit
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SPICE
• TODO show spice results of voltages
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Demonstration Chain
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Spice
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Conclude
• Cannot cascade degraded inputs into
gates.
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Admin
• Project
– Due Friday
• Midterm 2: Nov. 9th
– Week from Wednesday in the evening
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Idea
• There are other circuit disciplines
• Can use pass transistors for logic
– Even chains of pass transistors
– Sometimes gives area or delay win
• Do not cascade as easily as CMOS
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