Transcript ppt - SEAS
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 5: September 8, 2014 Transistor Introduction (first order) 1 Penn ESE370 Fall2014 -- DeHon Today • First order model • There are always Rs and Cs 2 Penn ESE370 Fall2014 -- DeHon Previously • Quasi-Static – inputs transition, circuit responds, and settles – Dynamic transition to roughly static states • DC/Steady-State – Ignore the capacitors • Zeroth-order allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits 3 Penn ESE370 Fall2014 -- DeHon Zero-th Order MOSFET • Ideal Switch Vgs > Vth conducts Vgs < Vth does not conduct Vth – threshold voltage • Gate draws no current from input – Loads input capacitively 4 Penn ESE370 Fall2014 -- DeHon Zero-th Order MOSFET IDS 5 Penn ESE370 Fall2014 -- DeHon First Order Model • Switch – Loads gate input capacitively • Cg – Has finite drive strength • Ron 6 Penn ESE370 Fall2014 -- DeHon Gate Output • Assume this is equivalent circuit for gate output state 7 Penn ESE370 Fall2014 -- DeHon Gate Output Load • What is Vout if gate is unloaded? 8 Penn ESE370 Fall2014 -- DeHon Gate Output Load • What happens to Vout when add a load? 9 Penn ESE370 Fall2014 -- DeHon Resistive Load • What happens when load is resistance? 10 Penn ESE370 Fall2014 -- DeHon Resistive Load • If loaded resistively, and resistive load is too strong (resistance too low) • Cause output voltage to drop 11 Penn ESE370 Fall2014 -- DeHon Capacitive Load • What happens when load is capacitance? 12 Penn ESE370 Fall2014 -- DeHon Capacitive Load • Capacitive load does not change the steady-state output voltage • Will effect the delay (settling time) 13 Penn ESE370 Fall2014 -- DeHon First Order Model • Switch – Loads gate input capacitively • Draw no steady-state current • Does not impact steady-state voltage • Impacts Delay – Has finite drive strength • Could form voltage divider with resistive load • Impacts Delay Penn ESE370 Fall2014 -- DeHon 14 First Order Model (vs. Vds) 15 Penn ESE370 Fall2014 -- DeHon First Order Model (vs. Vgs) 16 Penn ESE370 Fall2014 -- DeHon Refine to First Order 17 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) How are switches set in this case? 18 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) V2=Vdd Vout=0 19 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) V2=Vdd Vout=0 20 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) • Leaves an RC Circuit we can analyze ESE215 problem 21 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) What is equivalent circuit of load at V2? 22 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) What is equivalent output circuit for first pair of transistors driving V2? 23 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) What is relevant circuit? 24 Penn ESE370 Fall2014 -- DeHon Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) Vdd Gnd Penn ESE370 Fall2014 -- DeHon What is relevant circuit? 25 Zero-th Order Tells us how switches set (Vin=0) • Look at middle stage (V2) What is delay of this stage? (charging V2 when Vin switch Vdd0) 26 Penn ESE370 Fall2014 -- DeHon What more does first-order model tell us? • Delay • Quasistatic behavior • Voltage settling with resistive loads – At least some basis for reasoning 27 Penn ESE370 Fall2014 -- DeHon What is this leaving out? 28 Penn ESE370 Fall2014 -- DeHon What is this leaving out? 29 Penn ESE370 Fall2014 -- DeHon What leaving out? • What happens at intermediate voltages – Not rail-to-rail (not just gnd or Vdd input) • Details of dynamics, including… – Input not transition as step – Intermediate drive strengths change with Vgs • Isn’t really 0 current below threshold 30 Penn ESE370 Fall2014 -- DeHon Engineering Control • Vth – process engineer • Drive strength (Ron)– circuit engineer control with sizing transistors • Supply voltages (Vdd) – range set by process – detail use by circuit design 31 Penn ESE370 Fall2014 -- DeHon Engineering Control: Threshold 32 Penn ESE370 Fall2014 -- DeHon Engineering Control: Drive Strength 33 Penn ESE370 Fall2014 -- DeHon Rs and Cs 34 Penn ESE370 Fall2014 -- DeHon Wire Capacitance 35 Penn ESE370 Fall2014 -- DeHon Wire Capacitance A Cr0 d Penn ESE370 Fall2014 -- DeHon 36 Wire Resistance 37 Penn ESE370 Fall2014 -- DeHon Wire Resistance R Penn ESE370 Fall2014 -- DeHon L A 38 Wire Resistance • Sanity check – Wire twice as long = resistors in series – Wire twice as wide = resistors in parallel R Penn ESE370 Fall2014 -- DeHon L A 39 There are always Rs and Cs • • • • • Every wire (connection) has resistance Every wire has capacitance (Every wire has inductance) Modeling vs. discrete components Dominant effects – Rbig + Rsmall ≈ Rbig (Rwire << Ron)? – Cbig || Csmall ≈ Cbig (Cwire<<Cg) ? • Today more likely (Cwire>>Cg) 40 Penn ESE370 Fall2014 -- DeHon Big Ideas • MOSFET Transistor as switch • Purpose-driven simplified modeling – Aid reasoning, sanity check, simplify design • Analysis methodology – zero-th order to understand switch state (logic) – First-order to get equivalent RC circuit (delay) • New perspective on Rs and Cs 41 Penn ESE370 Fall2014 -- DeHon MOSFET 42 Penn ESE370 Fall2014 -- DeHon Admin • Normal Office Hours this week – Ron on Monday 7pm (Detkin) – Andre on Tuesday 4:15—5:30pm – Ron on Wednesday 7pm (Detkin) • Lecture on Wed. • Homework on Thursday • Lab on Friday (Ketterer) 43 Penn ESE370 Fall2014 -- DeHon