Transcript ppt - SEAS

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 19: October 22, 2010
Pass Transistor Logic
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Penn ESE370 Fall2010 -- DeHon
Today
• Pass Transistor Logic
– Muxes
– Performance
– Composition
– Logic
– Tristates
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Behavior
• O=S*A + S*/B
S
A
B
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Delay
• Assume R0/2 drive
• 10C0 load
• What else need to know?
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– Cdiff=CSB or CDB
– Assume Cdiff≈Cgate
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5
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Day 10
Capacitances
• GS, GB, GD, SB, DB, SD
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Day 10
Contact Capacitance
• n+ contacts are formed by doping = diffusion
• Depletion under contact
– Contact-Body capacitance
• Depletion around perimeter of contact
– Also contact-Body capacitance
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Day 10
Contact/Diffusion Capacitance
• Cj – diffusion depletion
• Cjsw – sidewall capacitance
• LS – length of diffusion
LS
Cdiff  C j LSW  C jsw 2LS  W 
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Delay
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5
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Delay
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CMOS Equivalent
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CMOS Delay
• O=S*A + S*/B
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What’s different?
• What’s different about the output?
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Output ok?
• Is the output usable?
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CMOS DC Transfer Function
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After CMOS Inverter
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What does this do?
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Cascade Functional?
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Voltage Drop
• Voltage drop across any number of
series transistors is one Vth
• Think about two series transistors as
one transistor of twice the length
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Day 9
Pinch Off
• When voltage drops below VT, drops
out of inversion
– Occurs when: VGS-VDS< VT
• Conclusion:
– current cannot increase with VDS once
VDS> VGS-VT
– current must adjust so that VDS= VGS-VT
– If current dropped to zero, then would
invert and conduct again…
Penn ESE370 Fall2010 -- DeHon
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Performance?
• Assume R0/2 drive
• 10C0 load
• Cdiff=Cgate
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2
5
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What does this do?
A
B
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Performance
• R0/2 drive
• 10C0 load
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2
5
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Performance
• R0/2 drive
• 10C0 load
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Not Isolating
• Does not isolate downstream capacitive load
• Stage delay now dependent on downstream
stages
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Class Ended Here
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Power Implications
• What’s the power impact of partial
swing?
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Back to Rail
• How make it go to rail?
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Transmission Gate
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Level Restorer
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Level Restorer
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Level Restore
• What issue arises here?
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Level Restore
• What issue arises here?
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Tristate
• Sometimes want to be able to not drive
a line
– Bus driven from different places
– I/O port – sometimes read, sometime write
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Tristate Driver
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Tri-State Drivers
Next week
• No new assignment now
– (will get new one after midterm)
• Class Monday
• Midterm Wednesday
– No lecture
– Midterm 7-9pm in this room
• Class Friday
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Penn ESE370 Fall2010 -- DeHon
Midterm
(Everything through today)
• Restoration
• Implement or
identify gate / logic
function
• Estimate
performance for
circuit
• Estimate/reduce
energy for circuit
• Size transistors in
gate/netlist
• Variation impact
• Scaling
• Ratio and pass tr
circuits fair game
• Synchronous/clockin
g not on midterm
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Ideas
• There are other logic disciplines
• We have the tools to analyze
• Pass Transistor Logic
– Possibly smaller, faster
– Not rail-to-rail
• Techniques to restore
– Cascading without buffering  slow
– Tristate Drivers
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