Transcript ppt - SEAS

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 13: October 3, 2012
Layout and Area
Penn ESE370 Fall 2012 -- Townley & DeHon
Today
• Coping with Variation (from last time)
• Layout
– Transistors
– Gates
• Design rules
• Standard cells
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Penn ESE370 Fall 2012 -- Townley & DeHon
Variation
• Margin for expected variation
• Must assume Vth can be any value in range
– Speed  assume Vth slowest value
Ion,min=Ion(Vth,max)
Probability Distribution
Id,sat (Vgs-Vth)2
VTH
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Penn ESE370 Fall2012 -- DeHon
Variation
• See a range of parameters
– L: Lmin – Lmax
– Vth: Vth,min – Vth,max
• Validate design at extremes
– Work for both Vth,min and Vth,max ?
– Design for worst-case scenario
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Penn ESE370 Fall2012 -- DeHon
Margining
• Also margin for
– Temperature
– Voltage
– Aging: end-of-life
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Penn ESE370 Fall2012 -- DeHon
Process Corners
• Many effects independent
• Many parameters
• With N parameters,
– Look only at extreme ends (low, high)
– How many cases?
• Try to identify the {worst,best} set of
parameters
– Slow corner of design space, fast corner
• Use corners to bracket behavior
Penn ESE370 Fall2012 -- DeHon
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Simple Corner Example
What happens
at various
corners?
350mV
Vthp
150mV
150mV
350mV
Vthn
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Penn ESE370 Fall2012 -- DeHon
Process Corners
• Many effects independent
• Many parameters
• Try to identify the {worst,best} set of
parameters
– E.g. Lump together things that make slow
• Vthn, Vthp, temperature, Voltage
• Try to reduce number of unique corners
– Slow corner of design space
• Use corners to bracket behavior
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Penn ESE370 Fall2012 -- DeHon
Range of Behavior
Probability Distribution
• Still get range of performances
• Any way to exploit the fact some are faster?
Delay
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Penn ESE370 Fall2012 -- DeHon
Probability Distribution
Speed Binning
Sell
Premium
Sell
Sell
nominal cheap
Discard
Delay
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Penn ESE370 Fall2012 -- DeHon
Layout
Penn ESE370 Fall 2012 -- Townley & DeHon
Transistor
Side view
Perspective view
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Penn ESE370 Fall 2012 -- Townley & DeHon
Layout
• Sizing &
positioning of
transistors
• Designer controls
W,L
• tox fixed for
process
– Sometimes
thick/thin oxide
“flavors”
Penn ESE370 Fall 2012 -- Townley & DeHon
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NMOS Geometry
L
W
Top view
Perspective view
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Penn ESE370 Fall 2012 -- Townley & DeHon
NMOS Geometry
L
S
G
• Color scheme
D
– Red: gate
– Green: source and drain
areas (n type diffusion)
W
Top view
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Penn ESE370 Fall 2012 -- Townley & DeHon
tox
• Transistors built by depositing materials
– Constant rate of deposition (nm/min)
– Time controls tox
• Oxides across entire chip deposited at same
time
– Same time interval
– thickness is (roughly) constant
– Process engineer sets value to:
• Assure yield
• What does tox control?
– Field strength  Vth, current
– Achieve Performance, minimize leakage
Penn ESE370 Fall 2012 -- Townley & DeHon
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NMOS vs PMOS
• Mostly talked about NMOS so far
– PMOS: “opposite” in some sense
– NMOS built on p substrate, PMOS built on n
substrate
– Name refers to bias/carriers when channel is
inverted
Penn ESE370 Fall 2012 -- Townley & DeHon
Rabaey text, Fig 2.1
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PMOS Geometry
L
S
G
• Color scheme
D
W
– Red: gate
– Orange: source and drain
areas (p type)
– Green: n well
• NMOS built on p wafer
n well
– Must add n material to
build PMOS
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Penn ESE370 Fall 2012 -- Townley & DeHon
Body Contact
• “Fourth terminal”
• Needed to set
voltage around
device
– PMOS: Vb = Vdd
– NMOS: Vb = GND
• At right: PMOS
(orange) with body
contact (dark green)
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Penn ESE370 Fall 2012 -- Townley & DeHon
Rotate
All but
PMOS
Transistor
90 degrees
Penn ESE370 Fall 2012 -- Townley & DeHon
Interconnect
• How to connect transistors
– Different layers of metal Intermediate
layers
• “Contact” - metal to transistor
• “Via” - metal to metal
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Penn ESE370 Fall 2012 -- Townley & DeHon
Interconnect
• How to connect transistors
– Different layers of metal Intermediate
layers
• “Contact” - metal to transistor
• “Via” - metal to metal
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Penn ESE370 Fall 2012 -- Townley & DeHon
Interconnect Cross Section
Penn ESE370 Fall 2012 -- Townley & DeHon
ITRS 2007
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Masks
• Define areas want to see in layer
– Think of “stencil” for material deposition
• Use photoresist (PR) to form the “stencil”
– Expose PR through mask
– PR dissolves in exposed area
– Material is deposited
• Only “sticks” in area w/ dissolved PR
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Penn ESE370 Fall 2012 -- Townley & DeHon
Masking Process
Mask
Silicon wafer
• Goal: draw a shape on the substrate
– Simplest example: draw a rectangle
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Penn ESE370 Fall 2012 -- Townley & DeHon
Silicon wafer
Masking Process
Mask
photoresist
• First: deposit photoresist
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Penn ESE370 Fall 2012 -- Townley & DeHon
Masking Process
• Expose through mask
– UV light
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Penn ESE370 Fall 2012 -- Townley & DeHon
Masking Process
• Remove mask and
develop PR
– Exposed area
dissolves
– This is “positive
photoresist”
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Penn ESE370 Fall 2012 -- Townley & DeHon
Masking Process
• Deposit metal through PR
window
– Then dissolve remaining PR
• Why not just use mask?
– Masks are expensive
– Shine light through mask to
etch PR
– Can reuse mask
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Penn ESE370 Fall 2012 -- Townley & DeHon
Logic Gates
• How to build
complete inverter?
– Connect NMOS,
PMOS using
metal
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Penn ESE370 Fall 2012 -- Townley & DeHon
Inverter Layout Example
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Penn ESE370 Fall 2012 -- Townley & DeHon
Inverter Layout Example
• Start with
PMOS, NMOS
transistors
• Space for
interconnect
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Penn ESE370 Fall 2012 -- Townley & DeHon
Inverter Layout Example
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Penn ESE370 Fall 2012 -- Townley & DeHon
Inverter Layout Example
• Add body
contacts
• Connect gates
of transistors
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Penn ESE370 Fall 2012 -- Townley & DeHon
Inverter Layout Example
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Penn ESE370 Fall 2012 -- Townley & DeHon
Inverter Layout Example
• Add contacts to
source, drain,
gate, body
• Connect using
metal (blue)
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Penn ESE370 Fall 2012 -- Townley & DeHon
Design Rules
• Why not adjacent
transistors?
– Plenty of empty
space
– If area is money,
pack in as much as
possible
• Recall: processing
imprecise
– Margin of error for
process variation
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Penn ESE370 Fall 2012 -- Townley & DeHon
Design Rules
• Contract between process engineer &
designer
– Minimum width/spacing
– Can be (often are) process specific
• Lambda rules: scalable design rules
– In terms of  = 0.5 Lmin (Ldrawn)
– Can migrate designs from similar process
– Limited scope: 45nm process != 1m
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Penn ESE370 Fall 2012 -- Townley & DeHon
Design Rules:
Some Examples
2


2
3
2
1.5
6
6
Legend
Penn ESE370 Fall 2012 -- Townley & DeHon
contact
n doping
metal 1
gate
via
p doping
metal 2
Layout Revisited
• How to
“decode” circuit
from layout?
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Penn ESE370 Fall 2012 -- Townley & DeHon
Layout to Circuit
• 1. Identify
transistors
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Penn ESE370 Fall
Fall2010
2012----DeHon
Townley & DeHon
Layout to Circuit
• 2. Add wires
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Penn ESE370 Fall 2012 -- Townley & DeHon
Layout to Circuit
• 2. Add wires
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Penn ESE370 Fall 2012
2010 -- Townley (DeHon)
& DeHon
Layout to Circuit
• 2. Add wires
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Penn ESE370 Fall 2012
2010 -- Townley (DeHon)
& DeHon
Layout to Circuit
• 2. Add wires
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Penn ESE370 Fall 2012
2010 -- Townley (DeHon)
& DeHon
Layout #2 (practice)
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Penn ESE370 Fall 2012 -- Townley & DeHon
Layout #2 (practice)
• How many
transistors?
– PMOS?
– NMOS?
• How connected?
– PMOS, NMOS?
• Inputs connected?
• Outputs?
• What is it?
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Penn ESE370 Fall 2012 -- Townley & DeHon
Standard Cells
• Lay out gates so that heights match
– Rows of adjacent cells
– Standardized sizes
• Motivation: automated place and route
– EDA tools convert HDL to layout
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Penn ESE370 Fall 2012 -- Townley & DeHon
Standard Cell Area
All cells
uniform
height
inv nand3
Width of
channel
determined
by routing
Cell area
Identify the full custom and standard cell regions on 386DX die
http://microscope.fsu.edu/chipshots/intel/386dxlarge.html
Penn ESE370 Fall 2012 -- Townley & DeHon
Admin
•
•
•
•
HW4 due Thursday
Lecture on Friday
Review on Sunday at 6pm
Exam on Monday
– No class at noon that day
Penn ESE370 Fall 2012 -- Townley & DeHon
Big Idea
• Layouts are physical realization of
circuit
– Geometry tradeoff
• Can decrease spacing at the cost of yield
• Design rules
• Can go from circuit to layout or layout to
circuit by inspection
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Penn ESE370 Fall 2012 -- Townley & DeHon