Transcript Low-Power SRAM Using 0.5 um Technology

Low-Power SRAM Using
0.6 um Technology
Andrew Ashworth
Jonathan Chen
Matt Williams
Introduction
• Metrics: Power(mW), Delay(ns), Area(mm2)
• Low Power SRAM:
(total power)2 * delay * area
• SRAM size of 1 Mb
• Word size of 32 bits
• One read or one write access per cycle
Clock
• Two-phase non-overlapping clock generator
CLK
CLK1
CLK2
Array Architecture
• Block Selector, Transmission Gates, and Positive
Edge Triggered Register
<0:3>
Word-line Enable Bit
<4:7>
<8:11>
<12:15>
A14A13A12A11A10
5:32
<16:19>
<20:23>
<24:27>
<28:31>
0
1
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31
Block Architecture
• Hierarchical word line with divided bit line
1
Local
WL
Local
WL
A 5A 4A 3A 2
4.5um
Local
BL
1.5um
1.5um
Local
BLB
4:16
4:16
Enable bit from
5:32 Decoder
Enable bit
1
4
Enable bit
1.5um
1
4.5um
A 9A 8A 7A 6
4
4:16
4:16
Transistors use 0.5 um technology. Sizes shown represent widths of devices.
Numbers shown by inverters are ratios relative to minimum sized inverter
4
To local
word-line
Block Architecture Continued
Global Bit-Line
Global Bit-Line Bar
from Figure 5
Divided bit line approach with 16 bit cells per local bit line
Drowsy Cache
•An extra 6t bit cell holds whether block is asleep or awake and
selects corresponding Vdd
•Requires extra dc-dc converters on chip
Layout
• Horizontal bit cell to maintain square block
• We should have learned SKILL
Challenges
• Drivers
• Clock generation – iterated through 3 designs
before finally settling on a pulsed NOR design.
• Designing sense amp enable driver
Simulation
• Extracted parasitic capacitances from layout to
build accurate array model
• Simulated model of one block to represent
entire array
• Began with worst case 50C and SS to find
stable clock
Results
• The SRAM correctly performed a write
followed by a read at all process corners, and
temperatures
• As VDD is scaled down, leakage power
decreases by orders of magnitude. We have
no reliable numbers as power simulations
returned unrealistic results for 5V VDD
Results II
Metric
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Total Size: about 500mm^2
Average Power: about 9mW
Delay: about 35ns
Total Metric: 1.458 million
Questions?