Transcript Bit-Line Leakage Cancellation: Design and Test Automation

Bit-Line Leakage Cancellation:
Design and Test Automation
Sudhanshu Khanna
April 22, 2010
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Deliverables
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Bit-Line Leakage Cancellation
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Schematic
Layout
On-Chip High Speed Testing
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Memory BIST
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BOTTOM – UP
DESIGN
TOP – DOWN
DESIGN
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Goals & Constraints:
L1 Cache design
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Achieve High Density
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How: More Bit-Cells, Less Periphery
Achieve High Speed
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How: Lower Read Time
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L1 bit-cells use Low-Vt transistors
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Memory-Vdd must be same as Core-Vdd
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=> Can’t use Multi-Vdd to increase performance
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Why is Bit-Line Leakage an Issue
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Challenges (Scaling issues)
 Lower Iread
 Higher Ileakage
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Only solution: Reduce # cells on a bit-line => Lower Density
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Why is Bit-Line Leakage an Issue
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SA differential = V(BL) – V(BLB)
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If BL leaks, differential lowers (data-dependent too)
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More time needed to generate same differential => Lower Speed
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Where is Bit-line leakage an
issue?
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Advanced technology nodes
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Issue: High Vt variation, high leakage
Result: Impact on performance
Sub-threshold memory
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Issue: Low Ion/Ioff
Result: Energy penalty due to higher required BL swing
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High Temperature Compliant Memories
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Alternative memories
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Bit-line Leakage Cancellation
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Sense leakage value during pre-charge
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Inject opposite current during read
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Drawbacks:
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V -> I conversion inaccuracies
Pre-charge to VDD – Vt required
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Agawa et al, 2001
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High Speed Testing Issues
Signal Analyzer
TESTER
~ 100 MHz
~ 20 MHz
1 GHz Inverter
OUTPUT PAD
~ 200 MHz
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You can make a FAST inverter, but
you cant see it work
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Memory BIST
High Speed Clock
F
S
M
Start
External Tester (Slow Testing)
Data generator
Address generator
Control generator
Done
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BIST
mode
Memory
Fail
M-BIST Design Flow
Algorithm
Behavioral Verilog: NC-Verilog
Structural Verilog: RTL Compiler
Place and Route: Encounter
Integration with Custom Memory: Virtuoso
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Top-Down Flow Issues Faced
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RTL Complier
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Encounter
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Assign Statements
Unused Nets connect to VDD, VSS
 Inputs of standard blocks e.g. Carry-In of Adder
 Unused bus signals: e.g. Z[4] of a bus Z[11:0]
< > vs
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Virtuoso:
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Global Signals
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Thanks for your time !
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