Transcript No Slide Title

Nov. 9, 2005
Device Sizing for Leakage Reduction in
Minimum Energy Circuits
Qiaoyan Yu and Paul Ampadu
ECE Department, University of Rochester, Rochester, NY
<qiaoyan,ampadu>@ece.rochester.edu
Abstract
Basic Performance
Subthreshold operation has gained much
attention for reducing energy consumption
of digital circuits.
9-Stage Ring Oscillator
In 180 nm technology, NMOS transistor attains
minimum drain leakage current at width=550nm,
while PMOS transistor does not.
Threshold voltage modulation due to
narrow-width effects leads to dependence
of leakage current on width.
NMOS transistor simulations in 180 nm
and 90 nm TSMC CMOS technologies
indicate that minimum leakage current does
not occur with minimum size transistor.
Similar behavior observed in 90 nm technology
9-stage ring oscillator achieves minimum
power at the size that yields minimum drain
leakage current. Power is reduced by
 up to 15.3% in 180 nm technology;
Power reduction by minimizing
leakage is more significant at low
voltages.
 up to 1.7% in 90 nm technology.
The implications of sizing for minimum
leakage on power, delay, and power-delay
product have been examined for
 inverter
 9-stage ring oscillator
Leakage reduction comparison
Introduction
Narrow-gate-width effects
Threshold voltage increases with width in
technologies that use
• Raised field-oxide isolation structures
• Semirecessed local oxidation isolation
Inverter
Sizing the NMOS transistor of an
inverter for minimum leakage current
yields a reduction in leakage power by
 58.1% in 180 nm technology;
up to 12.8% in 90 nm technology.
 Threshold voltage decreases with width in
technologies that use
• Fully recessed local oxidation isolation
• Trench isolation structures
The reduction in leakage power is
accompanied by increase in delay of
 5.3% in 180 nm technology;
 4.1% in 90 nm technology.
Parameters influencing drain current
1
W
I D  m nCox (VGS  VTH ) 2 (1  VDS ) Above threshold
2
L
W
I D  mn
L
 kT
 
 q
2
q (VGS VTH )
 qVDS

 exp skT (1  exp kT )(1  VDS ) Subthreshold

Relation of threshold voltage and size
Vth p
Vth L Vth w
Vth  Vth0 


Leff Weff Leff Weff
Empirical
Sizing for minimum leakage can save
energy at low activities.
 In 180 nm technology, PDP is minimum
at 0.5 mm width and 0.9 V supply voltage;
 In 90 nm technology, PDP is minimum at
0.2 mm width and 1.0 V supply voltage.
Conclusion
Drain leakage current may attain
minimum values for device sizes
other than the smallest.
NMOS
transistors
exhibit
a
distinctive minimum in leakage as a
function of width across technology
generations.
In low activity circuit blocks where
leakage dominates total energy,
additional energy saving may be
obtained through sizing.
Acknowledgement
Thanks to Prof. Martin Margala,
and EdISon Lab’s colleagues: Dr.
Amos Kuditcher, Bo Fu and David
Wolpert, University of Rochester.