Transcript Physics and Hardness Assurance for Bipolar Technologies

MURI
Device-level Radiation Effects
Modeling
Hugh Barnaby, Jie Chen, Ivan Sanchez
Department of Electrical Engineering
Ira A. Fulton School of Engineering
Arizona State University
Topics
• Target of Research
• Radiation Effect Modeling: A TCADbased approach
• Example: Drain-source leakage in deepsubmicron bulk CMOS
Goals
• Model the effects of TID and DD defects
on advanced device technologies
• Identify the continuing and emerging
radiation threats to these technologies
• Model the defects: implement physical
models, dynamics of buildup
• Radiation effects testing (Co60, neutrons, low
temperature testing)
Radiation Concerns
• Total ionizing dose
• Displacement damage
• Single event damage and micro-dose
Technologies and Techniques
• Ultra Thin Oxides
• Shallow Trench Isolation
• Buried Oxides
• Implants
• Heterojunctions
• Gate technologies
Device Categories
• Ultra Small Bulk CMOS
• Silicon on Insulator (dual gate operation)
• Strained Silicon CMOS
• SiGe HBTs
ASU has a strong relationship with FreeScale
semiconductor.
Effects
• Oxide Damage and Reliability
•
•
•
•
Defect buildup
Leakage
Breakdown
Annealing and other temperature dependent
processes
• Semiconductor Effects
•
•
•
•
Electrostatics
Carrier recombination and removal
Mobility effects
Annealing and other temperature dependent
processes
Testing
• Co60 g-sources
• ASU (100 rd/s, 1 rd/s, ~10mrd/s)
• UA (100 rd/s, 10 md/s)
• Neutron Sources (UA – Triga and Rabbit
Reactors)
• Low temperature Co60 irradiations (down to
70k)
TCAD Modeling and Simulation
TCAD Flow
Process and Layout
Description
Design
Bias Conditions
Process
Sim.
Device
Sim.
To
EDA
Circuit
Sim.
OPTIMIZE
STRUCTURE GEOMETRY
OPTIMIZE ELECTRICAL
PERFORMANCE
PROCESS
DEVICE
CIRCUIT
Ileak
NET DOPING
2D cross section of LOCOS
parasitic nMOSFET
POTENTIAL
2D potential contours
in parasitic nMOSFET
Vd
Leakage current vs.
drain voltage
SRAM Schematic including
parasitic nMOSFET element
Radiation Effects Modeling
Displace.
Damage
Total
Dose
heating, defect formation,
tunneling.
Strain effects, energy
to defect conv.,
doping profiles
carrier transport in
dielectric,
defect formation and
approximations
Defect precursors
Process and Layout
Description
Bias
Conditions
Process
Device
OPTIMIZE GEOMETRY
AND PRECURSORS
Example: D-S Leakage
Due to aggressive scaling into the deep sub-micron, the
threat of significant threshold voltage shifts caused by
charge buildup in the gate oxide has been reduced.
Instead threats have shifted elsewhere, such as drain-tosource leakage caused by charge buildup in the
isolation oxide (shallow trench – STI)
STI
shallow trench
isolation oxide
N+ Source
Polysilicon gate
N+ drain
Leakage
Leakage
+
++
+
+
+
++
+
+
TID effects on off-state leakage
1E-03
VG = 1.8 V
TSMC 0.18 m
NMOS
72 rad/s
Minimum Geometry
1E-05
3.2 nm/STI
• Increase in off-state
leakage (ID @ Vgs = 0V)
increases to 100nA after
400 krad of exposure.
50K
1E-07
100K
150K
1.E-06
1E-09
1E-11
1E-13
• Problem in SRAM arrays
(power, overheating, and
failure)
200K
1.E-07
IDoff (A)
Drain Current (A)
0
250K
1.E-08
1.E-09
300K
1.E-10
400k
1.E-11
500k
1.E-12
PA
250
300
350
400
Dose (krad(Si))
1E-15
-0.5
0
0.5
1
Gate Voltage (V)
After Lacoe NSREC SC 2003
1.5
2
TI-MSC1211 A/D Converter
5V
Supply
• 24-bit Delta-Sigma ADC
V5V
supply
Supply
Isupply
AVDD
• Intel 8051 microcontroller
DVDD
• Timers
Flash
memory
• Universal asynchronous receiver
and transmitter
REFIN
AIN+
AIN-
A/D
Processor
• Internal reference generator
RAM
• RAM, ROM, and flash memory
GND
UART
Comp.
Terminal
Temperature monitor, RTD
(resistant temperature device),
mounted on package
measure specifications
Offset Calibration
1
failure point
change in OCR (ppm)
0.5
0
post_rad
control
-0.5
• Bit-error output
for differential input
• High frequency data
represents noise
induced offsets
-1
-1.5
-2
0
5
10
15
20
25
30
• Mean value determined
by device mismatch,
temp variation, etc.
Dose (krads(Si))
Other specs include: full scale, and ENOB
Supply Current and Temperature
Digital Supply Current vs. DOSE
300
TID leads to increase in
operating temperature
of device.
200
150
Id
100
50
Package Temperature vs. DOSE
0
0
5
10
15
20
25
30
35
80
dose (krads (Si))
70
60
Temp (C)
Current (mA)
250
50
40
Temp
30
20
10
0
0
10
20
dose (krads (Si))
Field oxide leakage path
30
Photoemission Analysis
Increased power dissipation
and die temperature caused
by high static current density
in pre-charge devices of
SRAM array.
Vsupply
Field oxide leakage path
Mechanism
Increased current density reveals
impact of radiation-induced leakage
mechanism: the parasitic nMOSFET.
VDD
Precharge_n
WD0
bit
cell
bit
cell
bit
cell
bit
cell
WD1
bit
cell
bit
cell
bit
cell
bit
cell
WD127
bit
cell
bit
cell
bit
cell
bit
cell
B0
B0_n B1
Col(1:0)
B1_n B2 B2_n
B3
B3_n
Column select
b
bn
W_Rn
DIN
DIN_n
Sense_n
sense
amp
Dout(0)
Dout(1)
Dout(2)
Dout(7)
Parasitic nMOSFET
L
W
W
STI
“as drawn” nMOSFET
parasitic nMOSFET
VT
PRE-RAD
Due to its greater oxide thickness, the parasitic
nMOSFET has a much higher VT and lower drive
current compared to “as drawn” device.
POST-RAD
Due to its greater oxide thickness, oxide-charge
buildup in the parasitic nMOSFET is much greater,
causing large shifts in VT drive current.
“as drawn” nFET
parasitic nFET
VT (1013 )
VT (1012 ) VT (1011 ) VT (0)
Drive current
Drive current
Increasing TID
Parasitic nMOSFET Parameters
V CC_CIRCLE
“As Drawn” nFET
“As Drawn”
V CC_CIRCLE
Parasitic
Parasitic
nFET
tox
Weff
Vt
0
Circuit modeling of leakage
requires accurate extraction
of key parasitic parameters:
threshold voltage, effective
width, and oxide thickness
2D Modeling Approach
Standard 2-edge device
2D Cross-section along cutline
gate
Not
+ +
Drain
Cutline
Source
Not
+++
Gate
Si
+
+ STI
+
+
+
+
uniform oxide
charge (Not)
Modeling on IBM 0.13um 8RF CMOS
2D Modeling Results
Not = 5x1012 cm2 (uniform)
Vgs = 0.2V
+++
*
+
+
+
+
electron
+
inversion
+
layer
Combination of Not, gate bias,
and device properties creates
electron inversion layer at the
STI edge
Definition of Threshold Voltage
cutline
Silicon
0.6
0.4
Threshold voltage is the
gate voltage at which the
inversion potential () equals
the bulk potential.
Note: dependent on Not
density and cutline depth.
energy [eV]
0.2
bulk potential
(B)
0
-0.2
surface
potential
Inversion
potential
Ef –EfEiE
(0)
= = s
i(0)
-0.4
-0.6
-0.8
NOT=5E12 C/cm^2
NOT=2E12 C/cm^2
NOT=7E12 C/cm^2
Ef [eV]
STI
Threshold voltage [V]
Extracting Cox and tox
18
16
14
12
10
8
6
4
2
0
-2
VT of parasitic
Cox
Slope  Cox
Cross over
indicates TID
susceptibility
VT of “as drawn”
1
3
5
7
Oxide Trapped Charge (1012 cm-2)
 qNot

ΔVT
 4.6 x 10 8 F/cm 2
t ox 
 ox
Cox
 76 nm
Effective width (Weff.)
Parasitic nMOSFET width (Weff.) is dependent on oxide charge, gate bias,
and other parameters.
Not = 2x1012 cm2
Vgs = 0.2V
W(2)
Not = 5x1012 cm2
Vgs = 0.2V
W(5)
Not = 7x1012 cm2
Vgs = 0.2V
W(7)
Surface potential (Si/STI Oxide interface) [V]
Effective width (Weff.)
Weff is calculated at a
fixed gate bias and charge
density over a specified
depth (Wo).
s
0.7
0.6
0.5
Weff 
0.4
B
0.3
0.1
0
-0.005
0.005
0.015
0.025
Width (STI-FET) [um]
B

Wo
0
 42 nm
Weff
0.2
1
0.035
0.045
Sdw
Volumetric TID Simulations
How to relate device response to
dose, process, and bias conditions …
Sheet Charge
… use TCAD rad effects modeling to
generate NOT as function of precursors,
dose, dose rate, and electric field
Trapped Charge vol. distribution
+
+
+
+
+
+
New CMOS Processing Issues
Retrograde Channel doping
Non uniform doping profile used for
modeling variation in channel doping.
Strained silicon
“Both [IBM and Intel] introduced
strained silicon” in 90 nm.
- Semiconductor Insights
NS ~
1018
(ITRS 2002)
NB > 1019 (Brews TED 8-00)
d = 25 nm (ITRS 2002)
strained Si
channel
Impact of Retrograde
Without retrograde
- wide channel
- hi leakage
Examine leakage
channel inside box
With retrograde
- thin channel
- lo leakage
Will D-S leakage be a
problem for 90 nm?