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Slow Wires, Hot Chips, and Leaky Transistors:
New Challenges in the New Millenium
Norm Jouppi
Compaq - WRL
Disclaimer: The views expressed herein are the views of Norm
and are not statements by Compaq Computer Corporation
Slow Wires
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Wires have been slow before (Cray’s computers)
It is not the end of the world
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Cray-1 core < 1.5M transistors
Designers need to pay attention
Machine architecture is affected
Opportunity for innovation:
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CMP makes more sense
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Formerly slow inter-chip MP communication gets faster
Hot Chips
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Chips have been hot before
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E.g., 115W BIPS-0
It is not the end of the world
Designers need to pay attention
Opportunity for innovation:
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Low-power computing (i.e., running off a battery) will
not scale well
Now pick only 1 (instead of 2) out of 3:
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More function
Lower power
Higher clock speed
Background: Leaky MOS Transistors
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Two types of leakages
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Subthreshold conduction
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Leakage between source and drain
Like having a dimmer light switch
Carver Mead has been exploiting for years
Many possible ways to “fix”: SOI, low temp, …
Gate oxide leakage
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Leakage between gate and source or drain
Like having a “hot” light switch handle
Over last 25 years, Tox = Le / 45
Tox = 2.1nm for 0.10um process
Alternative gate dielectrics?
Prognosis: Leaky Transistors
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Transistors have been leaky before (BJTs)
It is not the end of the world
Designers need to pay attention
Opportunity for innovation:
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New CAD tools at the circuit level
Need separate gate processing for memory core
Traditional memory may not scale as well
Exacerbates the power problem
Real Problem: Design Complexity
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Design team size > 250 people for flagship uP
Design team growing 1/feature size
Designs take longer and have fewer changes
Hennessy’s verification to design team ratio 
ROI negative:
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200people x 3years x 167K$/personyear = 100M$
NRE/unit = 1K$ for 100,000 units
“Consolidation” has been and will continue
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In the number of architectures
In the number of distinct designs
Increasing NRE - Example: Mask Cost
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A mask set used to cost less than $25K
EUV mask sets may cost >1M$
Raises barrier to implementation in latest tech
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Standard uP: flagship, DSP, embedded
Standard RAM: DRAM, Non-Vol, SRAM?
FPGA’s
? ASICs
SOC
Custom-fit
? VLSI project chips via maskless tech
Summary
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+ Lots of opportunities for research
- ROIC (human, $) for implementation
decreasing
More and more things will be technically
feasible but economically unjustifiable