Transcript understanding gate leakage current developing circuit techniques

A Class presentation for VLSI
course by :
Maryam Homayouni
Based on the work presentation
“ANALYSIS & MITIGATION OF CMOS GATE
LEAKAGE”
Rahul M.Rao, Richard B. Brown University of Michigan
Kevin Nowka, Jeffry L. Burns IBM Austin Research Lab
This Work focuses on:
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understanding gate leakage current
developing circuit techniques for
total leakage minimization
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Input vector control
circuit reconfiguration techniques for total
leakage minimization of static and
dynamic circuits
design guidelines for optimal device size
selection for stacked sleep devices in an
enhanced MTCMOS configuration
Introduction
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Leakage component increase
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Device dimensions and
Threshold voltage Scaling
sub-threshold leakage
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gate oxide thickness scaling
gate leakage current
Leakage minimization
techniques which consider
Gate Leakage:
Boosted-gate MOS
 PMOS dominated[4]
 Gate leakage effect on circuit
performance and dynamic behavior of the floating body in
SOI
devices was examined in [5,6]
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Gate Leakage Analysis
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Gate leakage = exponential
function of the electric field
across the gate oxide
gate
leakage current shows
exponential dependence on VGS
high gate bias:
drain-to-source bias
gate leakage current
Low gate bias:
drain-to-source bias
gate leakage current
Gate leakage current is
insensitive to body node
VGS & VGD determine its gate
leakage
Gate leakage estimation
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bias conditions seen by a
device in a circuit depend on
its position in the circuit and
the applied input vector
a device exhibits gate leakage
only when there exists a
potential difference between
the gate & drain/source
terminals of the device
The gate leakage of any device
in the circuit can be estimated
from its bias state if there
exists a conducting path from
its device terminals to the
supply rails
The total gate leakage of the
circuit can be computed as the
sum of the gate leakage of the
individual devices
Leakage estimation in NAND3
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Assumption: the internal
nodes attain full logic levels
(i.e., are either at VDD or
VSS)
gate leakage is negligible if
no conducting path exists
from the device terminals to
the supply-rails
As seen, the leakage
estimates obtained by this
method are very accurate,
with an average error of less
than 1% and a maximum
error of less than 2%.
Leakage minimization techniques
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Transistor Stacks
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The sub-threshold leakage
through the transistor stack
is minimized when all of the
devices in the stack are
turned ‘OFF’(<000>)
All of the PMOS devices
have high Vgd and Vgs
High field across the gate
oxide causing gate leakage
and increase due to greater
width of PMOS devises

To reduce gate leakage, it is
necessary to maintain the
terminals of most of the
devices at the same
potential<110>
Transistor Stack
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The total leakage for
some of these vectors is
clearly dominated by the
gate leakage component
<110> is the minimum
total leakage state for
Nand3 cell
it is necessary to
reevaluate conventional
leakage minimization
schemes and input vector
assignments to account
for the effect of gate
leakage
Enhanced MTCMOS Scheme
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design guidelines for
optimal device size selection
for total leakage
minimization using stacked
sleep devices in an
MTCMOS configuration by
taking into consideration
the effect of gate leakage in
active and standby modes
In an enhanced MTCMOS
configuration ,sub-threshold
leakage is reduced in sleep
mode due to the added
effect of stacking of high
threshold voltage
transistors
..Enhanced MTCMOS Scheme
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maximum savings in subthreshold leakage are
obtained if the devices in the stack are sized as:
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the lower device in the stack is bigger than the upper
device
an increased negative gate-to-source bias and a
reduced drain-to-source bias (i.e. reduced DIBL) for
the upper device resulting in reduced sub-threshold
leakage.
The average gate leakage is always greater than that
for the MTCMOS configuration
..Enhanced MTCMOS Scheme
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The stacked sleep devices can also be
sized to maximize he savings in gate
leakage factor as
Thus the lower device is required to be
bigger than the upper ones
a lower gate leakage in the off state
optimizing for gate
leakage is nearly identical to optimizing
for total leakage
Test circuits
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test circuits have been implemented in a sub 0.1µm
advanced SOI process. An 8- bit Brent Khung adder
has been used as a design vehicle and has been
implemented in various dynamic circuit configurations,
with MTCMOS and various enhanced MTCMOS
configurations having sleep device stack optimized for
sub-threshold and gate leakage.
CONCLUSION
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growing importance of gate leakage current
efficient technique for gate leakage estimation
that is accurate to within 5% of SPICE simulation
results
Optimal leakage reduction vectors for transistor
stacks
design guidelines
for optimal device size selection for stacked sleep
devices
in an enhanced MTCMOS configuration
optimizing for gate leakage is nearly identical to
optimizing for total leakage.
Original References
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[1] International Technology Roadmap for Semiconductors, 2001 Edition
[2] H. Tseng, et.al, “Silicon Nitride Gate Dielectric for Advanced Technology,” Proc. International
Conference on Solid State and Integrated Circuits Technology", pp. 278- 82, 2000.
[3] T. Inukai, et.al, “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve
Leakage-Free Giga-scale Integration,” Proc. CICC, pp. 409-412, 2000.
[4] F. Hamzaoglu and M. Stan, “Circuit-Level Techniques to Control Gate Leakage for sub-100nm
CMOS,” Proc. ISLPED, pp. 60-63, 2002.
[5] C. T. Chuang and R. Puri, “Effect of Gate-to-Body Tunneling Current on Pass-Transistor Based
PD/SOI CMOS Circuits,” IEEE International SOI Conference, pp. 121-122, 2002.
[6] C. Choi, K. Nam, Z. Yu and R. Dutton, “Inpact of Gate Direct Tunneling Current on Circuit
Performance: A Simulation Study,” IEEE Trans. On Electron Devices, vol. 48, no. 12, pp. 28232839, 2001.
[7] S. Mutoh, et.al, “1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold
Voltage CMOS,” IEEE Journal of Solid State Circuits, vol. 30, no. 8, pp. 847-854, 1995.
[8] K. Das, et.al, “New Optimal Design Strategies and Analysis of Ultra-Low Leakage Circuits for
Nano- Scale SOI Technology,” Proc. ISLPED, pp. 168-171, 2003.
[9] K. Yang, et.al, “Edge Hole Direct Tunneling Leakage in Ultrathin Gate Oxide p-Channel
MOSFETs,” IEEE
Trans. On Electron Devices, vol. 48, no. 12, pp. 2790- 2795, 2001.
[10] R. Troutman, et.al, “VLSI limitations from draininduced barrier lowering,” IEEE Journal of
Solid State Circuits, vol. 14, no. 2, pp. 383-391, 1979.
[11] R. Rao, J. Burns, A. Devgan and R. Brown, “Efficient Techniques for Gate Leakage
Estimation,” Proc. ISLPED, pp. 100-103, 2003.
[12] R. Rao, J. Burns and R. Brown, “Circuit Techniques for Gate and Sub-Threshold Leakage
Minimization in Future CMOS Technologies” Proc. ESSCIRC, pp. 2790-2795, 2003.
[13] R. Rao, J. Burns, R. Brown, “Analysis and Optimization of Enhanced MTCMOS Scheme,”
Proc. International Conference on VLSI Design, pp. 2790- 2795, 2004.
December 2004