Transcript Circuit B

HOMEWORK 5-1
如图所示逻辑链，写出当A处的输入从1翻转为0时的传输延迟
表达式。
1
0
HOMEWORK 5-2
Sizing a chain of inverters.
a. In order to drive a large capacitance (CL = 20 pF) from a minimum size
gate (with input capacitance Ci = 10fF), you decide to introduce a twostaged buffer as shown in figure below. Assume that the propagation
delay of a minimum size inverter is 70 ps. Also assume that the input
capacitance of a gate is proportional to its size. Determine the sizing of
the two additional buffer stages that will minimize the propagation delay.
b. If you could add any number of stages to achieve the minimum delay,
how many stages would you insert? What is the propagation delay in this
case?
HOMEWORK 5-3
一个CMOS工艺的对称反相器特性参数为：Cox=8fF/um2，
Wn=2.2um ，L=0.4um ，r=2.6 ，并且VTn=│VTp│。用
它作为驱动CL=38pF的逻辑链的输入级。
a. 计算反相器的输入电容C1
b. 应用理想的尺寸放大原理求该逻辑链的级数。
C1
1
2
3
N-1
N
R1
k1
CL
k2
k3
kN-1
kN
HOMEWORK 5-4
如图所示逻辑链是以r=2.5的工艺制造的对称门路。采用逻辑努
力技术，求出使该逻辑链延时最小所需的每级的相对尺寸。
C=0.1CL
CL
HOMEWORK 5-5
A
3fF
X
B
Y
Z
W
V
100fF
a)Draw the schematic of the 3-input NAND gate, and size all
transistors such that the worst-case delay is equal to that of a
minimum sized 2/1 inverter. Find the logical effort (g) of the 3-input
NAND gate.
b)For the logic path from node (A) to node (B) shown in the figure
above, find the path branching effort, path electrical effort, path
logical effort, and total path effort. What is the optimum effort per
stage for minimizing delay?
c)Find the input capacitances {X, Y, Z, W, V} necessary for each of
the gates in the path in order to achieve the optimum effort per stage.
HOMEWORK 5-6
G2
A
G4
G1
B
G6
G3
C
G5
D
Circuit A is an AND4
implemented as a NAND2
chain while Circuit B
implements the same
function using a 4 input gate.
50
fF
Circuit A
A
B
C
D
G2
G1
Circuit B
50
fF
Size circuit A and circuit B for minimum delay with Cin of 3 fF and
Cout of 50 fF. Report your answer in terms of the input capacitance
seen at each gate.