Transcript ELE2
ELE2 DIGITAL REVISION NOTES Bistable Latch +Vs S +Vs R Q _ Q • When the SET input is briefly taken to logic 0, the Q output will become logic 1 and the Q output will become logic 0. • When the RESET input is now briefly taken to logic 0, Q will become logic 0 and the Q will become logic 1. NAND Gate Monostable +Vs R1 Vin TRC Y X C V R Vout 0V • When input of gate X goes low the output of gate X goes high. • This starts to charge capacitor C through resistor R and so makes the input of gate Y high. • The output of gate Y goes low, which is fed back to gate X so keeping its output high. • C charges through R until the input voltage to gate Y is below half of the supply voltage. • The output of gate Y goes high, making output of gate X low, circuit resets. +Vs NAND Gate Astable R1 C R control Y X V1 V2 Vout T2RC f=1/T 0V • Control input to first NAND gate goes high. • Output of first NAND gate goes low, output of astable goes high. • Capacitor discharges and charges in opposite direction. • Until voltage at input to first NAND gate <+Vs/2. • Output of astable switches state. • Capacitor charges in opposite direction. • Process repeats as long as control is high. D-Type Flip-Flop D S Q >CK R Q CK D 0 0 0 1 0 1 Q Q Q 0 1 Q Q Q 1 0 • S sets Q to 1, R resets Q to 0. Not dependent on the state of the clock, CK. • On the rising edge of CK, Q is set to the logic state of D. Data Latch D0 D S Q Q0 >CK R Q D1 D S Q Q1 >CK R D2 D Q S Q Q2 >CK R D3 D S Q Q >CK R CK Q Q3 • The data to be stored in the latch is set up on inputs D0 to D3. • When the data is steady, a short pulse is applied to the clock inputs. • The data is stored in the latch on the rising edge of the clock pulse. Shift Register Q0 Q1 Q2 Q3 logic 0 data input D S Q >CK D S Q >CK R Q D S Q >CK R Q D S Q >CK R Q R Q logic 0 clock input • On the rising edge of each clock pulse, the data from a Dtype flip-flop is stored in the next D-type flip-flop. • This data transfer occurs all of the way along the shift register. • Data from the output of the last flip-flop is lost. • New data applied to the input of the first flip-flop is taken into the shift register. Divide by 2 Counter D S Q output >CK input R Q • To make a flip-flop toggle:• Both Set and Reset are connected to 0 • D is connected to Q • The D input is then always opposite to Q and so toggling occurs on each successive clock pulse. Q0 D S Q >CK 4-bit Counters Q1 S Q D >CK Q2 D S Q >CK D Q3 S Q >CK input R Q logic 0 R Q R Q R Q all S inputs connected to logic 0 • D to Q • All Resets joined together • CK to previous Q for down counter and Q for an up counter • All resets joined together and connected to 0 Modulo-n Counters Q0 D S Q >CK all S inputs connected to logic 0 Q1 Q2 D S Q >CK D S Q >CK Q3 D S Q >CK input R Q R Q R Q R Q • Only up-counters. • AND gate output connected to reset. • AND gate inputs connected to appropriate Q outputs. • 5, Q0 & Q2 6, Q1 & Q2 10, Q1 & Q3 12, Q2 & Q3 Boolean Algebra • Commutative Laws: • A+B=B+A A·B=B·A • Associative Laws: • A + (B + C) = (A + B) + C A ·(B · C) = (A · B) · C • Distributive Law: • A · (B + C) = A · B + A · C • De Morgan's theorem A B AB A B AB Boolean Identities A A A AA A A A 0 A A 1 A 1 A A 1 1 A0 0 A0 A A AB A A (A B) A AA Karnaugh Maps BA 00 01 11 10 DC 00 1 0 1 1 01 0 1 0 1 11 0 1 0 1 10 1 0 0 1