Transcript PPT - SEAS - The George Washington University

The George Washington University
School of Engineering and Applied Science
Department of Electrical and Computer Engineering
ECE122 – 30
Lab 2: NAND gate design using CMOS
Jason Woytowich
Ritu Bajpai
Modified September 11, 2007
Propagation Delay
• Propagation Delay is the amount of time it
takes a change of input to appear as a
change on the output.
• Propagation Delay is measured from the
50% point on the input signal to the 50%
point on the output.
Input
Output
tpHL
Transition time
• High-low and low high transition times at
the output of a gate are defined as tHL and
tLH between the 10% and 90% points.
90%
10%
tLH
90%
10%
tHL
Gate Delay
• The load capacitance severely affects the
gate delay.
Inv1
Inv2
SCMOS Library
• Scalable CMOS Library
• Contains (just about) every digital logic
component you need to build anything.
• And, Or, Xor, Nand, Nor, Xnor, Inv, Buf,
Flip-flops, Pads, Capacitors, Resistors
• Each of these components has a specific
layout mapped to it.
• It does not layout individual transistors.
Objective for our simulation
• Create a NAND gate using p and n
MOSFET and testing its performance.
• Testing the performance of a NAND gate
from SCMOS library.
• Comparing the performance of the two
NAND gates.
Note the parameters
W=22u and L=2u
Note: In order of appearance the values
inside the brackets are lower pulse
voltage, higher pulse voltage, pulse
delay, rise time, fall time, pulse width,
pulse period.
tpHL
tpLH
Analysis/Result
• Record the rise time and fall time of both
the NAND gates.
• Is the rise time and fall time of each gate
same, if no then why?
• Is the rise time and fall time of both the
gates similar to each other, if no then what
could be the probable reasons for the
difference?
Analysis/Result
• Repeat the simulation to create a NOR
gate using CMOS.
• In the test circuit, replace your NOR gate
by the NOR gate in SCMOS library.
• Record the waveform in the two cases and
make the similar observations as you
made for NAND gate.