Transcript Chapter 2 - Part 1 - PPT - Mano & Kime

Logic and Computer Design Fundamentals
Lecture 11 – Design
Concepts
Charles Kime & Thomas Kaminski
© 2004 Pearson Education, Inc.
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Outline
 Hierarchical Design
 Technology Parameters
•
•
•
•
Propagation Delay
Delay Models
Fan-out
Cost
 Positive and Negative Logic
 Design Tradeoffs
Chapter 3 - Part 1
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Combinational Circuits
 A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
 A block diagram:
m Boolean Inputs
Combinatorial
Logic
Circuit
n Boolean Outputs
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Hierarchical Design
 To control the complexity of the function mapping inputs to
outputs:
• Decompose the function into smaller pieces called blocks
• Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
• Any block not decomposed is called a primitive block
• The collection of all blocks including the decomposed ones is a
hierarchy
 Example: 9-input parity tree (see next slide)
•
•
•
•
Top Level: 9 inputs, one output
2nd Level: Four 3-bit odd parity trees in two levels
3rd Level: Two 2-bit exclusive-OR functions
Primitives: Four 2-input NAND gates
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Hierarchy for Parity Tree Example
X0
X1
X2
X3
X4
X5
X6
X7
X8
9-Input
odd
function
ZO
(a) Symbol for circuit
X0
A0
X1
A1
X2
A2
X3
A0
3-Input
odd B O
function
X5
3-Input
A 1 odd B O
function
A2
X6
A0
X7
A1
X8
A2
X4
A0
A1
A2
3-Input
odd B
O
function
ZO
3-Input
odd B O
function
(b) Circuit as interconnected 3-input odd
function blocks
A0
A1
BO
A2
Design requires:
4 X 2 X 4 = 32 2-input NAND gates
(c) 3-input odd function circuit as
interconnected exclusive-OR
blocks
(d) Exclusive-OR block as interconnected
NANDs
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Reusable Functions and CAD
 Whenever possible, we try to decompose a complex
design into common, reusable function blocks
 These blocks are
• verified and well-documented
• placed in libraries for future use
 Representative Computer-Aided Design Tools:
•
•
•
•
Schematic Capture
Logic Simulators
Timing Verifiers
Hardware Description Languages
 Verilog and VHDL
• Logic Synthesizers
• Integrated Circuit Layout
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Top-Down versus Bottom-Up
 A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
 A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
 Designs usually proceed from both directions
simultaneously
• Top-down design answers: What are we building?
• Bottom-up design answers: How do we build it?
 Top-down controls complexity while bottom-up focuses
on the details
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Integrated Circuits
 Integrated circuit (informally, a “chip”) is a
semiconductor crystal (most often silicon)
containing the electronic components for the digital
gates and storage elements which are
interconnected on the chip.
 Terminology - Levels of chip integration
•
•
•
•
SSI (small-scale integration) - fewer than 10 gates
MSI (medium-scale integration) - 10 to 100 gates
LSI (large-scale integration) - 100 to thousands of gates
VLSI (very large-scale integration) - thousands to 100s of
millions of gates
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Technology Parameters
 Specific gate implementation technologies are
characterized by the following parameters:
• Fan-in – the number of inputs available on a gate
• Fan-out – the number of standard loads driven by a gate output
• Logic Levels – the signal value ranges for 1 and 0 on the inputs and
1 and 0 on the outputs (see Figure 1-1 of textbook)
• Noise Margin – the maximum external noise voltage superimposed
on a normal input value that will not cause an undesirable change
in the circuit output
• Cost for a gate - a measure of the contribution by the gate to the
cost of the integrated circuit
• Propagation Delay – The time required for a change in the value of
a signal to propagate from an input to an output
• Power Dissipation – the amount of power drawn from the power
supply and consumed by the gate
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Propagation Delay
 Propagation delay is the time for a change on an input
of a gate to propagate to the output.
 Delay is usually measured at the 50% point with
respect to the H and L output voltage levels.
 High-to-low (tPHL) and low-to-high (tPLH) output signal
changes may have different propagation delays.
 High-to-low (HL) and low-to-high (LH) transitions are
defined with respect to the output, not the input.
 An HL input transition causes:
• an LH output transition if the gate inverts and
• an HL output transition if the gate does not invert.
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Propagation Delay (continued)
=
 Propagation delays measured at the midpoint
between the L and H values
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Propagation Delay Example
OUT (volts)
IN (volts)
 Find tPHL, tPLH and tpd for the signals given
tpd=1.4
tPHL=1.4
tPLH=1.
1
t (ns)
1.0 ns per division
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Delay Models
 Transport delay - a change in the output in
response to a change on the inputs occurs after
a fixed specified delay
 Inertial delay - similar to transport delay,
except that if the input changes such that the
output is to change twice in a time interval less
than the rejection time, the output changes do
not occur.
• Models typical electronic circuit behavior, namely,
rejects narrow “pulses” on the outputs
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Delay Model Example
A
B
A B:
No Delay
(ND)
Transport
Delay (TD)
a b
c d e
Inertial
Delay (ID)
0
2
4
6
8
10
12
14
16 Time (ns)
Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns
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Fan-out
 Fan-out can be defined in terms of a
standard load
• Example: 1 standard load equals the load
contributed by the input of 1 inverter.
• Transition time -the time required for the
gate output to change from H to L, tHL, or
from L to H, tLH
• The maximum fan-out that can be driven by
a gate is the number of standard loads the
gate can drive without exceeding its specified
maximum transition time
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Fan-out and Delay
 The fan-out loading a gate’s output affects
the gate’s propagation delay
 Example:
• One realistic equation for tpd for a NAND
gate with 4 inputs is:
tpd = 0.07 + 0.021 SL ns
• SL is the number of standard loads the gate is
driving, i. e., its fan-out in standard loads
• For SL = 4.5, tpd = 0.07 + 0.021*4.5 = 0.165 ns
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Cost
 In an integrated circuit:
• The cost of a gate is proportional to the chip area
occupied by the gate
• The gate area is roughly proportional to the number
and size of the transistors and the amount of wiring
connecting them
• Ignoring the wiring area, the gate area is roughly
proportional to the gate input count
• So gate input count is a rough measure of gate cost
 If the actual chip layout area occupied by the
gate is known, it is a far more accurate measure
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Positive and Negative Logic
 The same physical gate has different logical
meanings depending on interpretation of the
signal levels.
 Positive Logic
• HIGH (more positive) signal levels represent Logic 1
• LOW (less positive) signal levels represent Logic 0
 Negative Logic
• LOW (more negative) signal levels represent Logic 1
• HIGH (less negative) signal levels represent Logic 0
 A gate that implements a Positive Logic AND
function will implement a Negative Logic OR
function, and vice-versa.
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Positive and Negative Logic (continued)
 Given this signal level table:
Input
X Y
L L
L H
H L
H H
 What logic function is implemented?
Positive (H = 1)
Logic
(L = 0)
0 0
0
0 1
1
1 0
1
1 1
1
Negative
Logic
1 1
1 0
0 1
0 0
Output
L
H
H
H
(H = 0)
(L = 1)
1
0
0
0
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Positive and Negative Logic (continued)
 Rearranging the negative logic terms to
the standard function table order:
Positive (H = 1)
Logic
(L = 0)
0 0
0
0 1
1
1 0
1
1 1
1
OR
Negative
Logic
0 0
0 1
1 0
1 1
(H = 0)
(L = 1)
0
0
0
1
AND
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Logic Symbol Conventions
 Use of polarity indicator to represent use of
negative logic convention on gate inputs or
outputs
XY Z
X
Y
CKT
Z
Logic Circuit
X
Y
Z
X
Y
LL
LH
HL
HH
L
H
H
H
Z
Positive Logic Negative Logic
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Design Trade-Offs


Cost - performance tradeoffs
Gate-Level Example:
•
•
•
NAND gate G with 20 standard loads on its output has a delay
of 0.45 ns and has a normalized cost of 2.0
A buffer H has a normalized cost of 1.5. The NAND gate driving
the buffer with 20 standard loads gives a total delay of 0.33 ns
In which if the following cases should the buffer be added?
1.
2.
3.


The cost of this portion of the circuit cannot be more than 2.5
The delay of this portion of the circuit cannot be more than 0.40 ns
The delay of this portion of the circuit must be less than 0.30 ns
and the cost less than 3.0
Tradeoffs can also be accomplished much higher in the design
hierarchy
Constraints on cost and performance have a major role in making
tradeoffs
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Summary
 Hierarchical Design
 Technology Parameters
•
•
•
•
Propagation Delay
Delay Models
Fan-out
Cost
 Positive and Negative Logic
 Design Tradeoffs
Chapter 3 - Part 1
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