Transcript An ASIC Design Methodology with Predictably Low Leakage

Predictably Low-Leakage ASIC
Design using Leakage-immune
Standard Cells
Nikhil Jayakumar
Sunil P. Khatri
University of Colorado at Boulder
Introduction
 Process feature sizes / operating voltages are
diminishing relentlessly.
 Threshold voltages of the MOS devices reduced
along with operating voltages to satisfy speed
requirements.
 Leakage (sub-threshold) currents increase as a
consequence
 Low leakage crucial for portable electronics to
ensure long battery life.
Introduction…2
 Saturation Current Equation:
Ids = K(W/L)(Vgs –VT)2(1+ Vds) ………….(1)
 Sub-threshold Current Equation:
Ids = (W/L)I0e(Vgs-VT-Voff/vT)(1-e(-Vds/VT))….(2)
 From equation(1): need to reduce threshold
voltage VT with supply voltage to maintain Ids
 From equation(2): decreasing VT increases
leakage current exponentially.
Previous Work
 DTMOS: Dynamic Threshold MOS. Device gate
connected to bulk (Assaderaghi et. al.)
 Results in high-speed switching and low-leakage
through body effect control.
 Drawback:
 Applicable only when VDD lower than the
diode turn-on voltage.
• Increased gate capacitance slows the device
down.
• Proposed for partially depleted SOI designs.
• Not easily modified to work for other
processes
Previous work…2
 VTCMOS: Variable threshold CMOS (Kuroda et.
al.)
 Device VT controlled by dynamically modifying the
device bulk voltage
 Drawbacks:
 Need complex circuitry to generate and control
the bulk voltages.
 Cannot be applied to fully depleted SOI, hard
to apply to partially depleted SOI.
 With future processes the body effect coefficient () will reduce
Previous work…3
 SCCMOS: Super Cut-Off CMOS (Kawaguchi et. al.)
 Gate of PMOS device (which gates the VDD
supply) overdriven during standby operation reduces leakage dramatically.
 Drawback:
 Complex circuitry required to generate the
special voltages.
Previous Work…4
 MTCMOS: Multi-threshold CMOS. (Kao et.al.)
 ”Power switches” (high VT MOS devices) added between
the supplies and the power pins of the circuit.
 Delay increased (controlled by sizing power switches
appropriately). Sizes of power switches for individual
logic cells is large.
 Device sizing algorithm (based on mutually exclusive
discharging of gates) can be used for groups of cells to
reduce the size of power switches.
 Drawbacks:
 Device sizing algorithm works well for regular logic.
 Leakage current unpredictable since internal nodes float
during standby operation
 Memory elements need separate supplies.
Our Approach
 Ensure that supply voltage applied across more
than one device and at least one of them is high
VT.
 Ensure that output of each cell is either logic-0 or
logic-1 in standby.
 No floating internal nodes.
 Allows precise estimation of circuit leakage.
 If input vector to gate (in standby) is known:
 We know which stack (pull-up / pull-down) is
leaking.
 Only one power switch device (PMOS or NMOS)
required.
Our Approach…2
 So we need two variants of each gate – the “H”
and “L” versions
 “H” cell: Inputs (in standby mode) such that
output is logic-1
 Leakage is in pull-down stack
 Minimize leakage by gating GND supply with high VT
NMOS device
 “L” cell: Inputs (in standby mode) such that output
is logic-0
 Leakage is in pull-up stack
 Minimize leakage by gating the VDD supply with a
high VT PMOS device
Example – NAND3
NAND3 (H, L variants)
Layout Floor plan
standby
standby
Regular Cell
L variant
H variant
 Routing standby signals done automatically (by
abutment).
 H,L use unmodified cell core from regular cell
 Minimizes re-design effort
Sample layout (NAND3-L)
standby
GND rail
VDD rail
standby
Process parameters and
sizing
 Used bsim100 predictive 0.1um model cards for
our experiments
 SPICE and MAGIC used for cell design and layout
 For MTCMOS and H/L gates, the supply gating
transistors sized such that delay penalty less than
15% (over the unmodified cell)
 Up-sizing transistors inside cell core can result in
smaller delay and area penalties.
 We did not modify cell core
Design Methodology
 Design flow using H/L cells very similar to
traditional standard cell based flow:
 Optimize and map to standard cell library (SIS).
 Given primary input assignment in standby mode:
 Simulate circuit, find output value of each gate.
 Replace with H / L variant of the gate.
 Decision made in time linear in size of circuit.
 Regular cells from UCBerkeley.
 Gates used:
 INVA, INVB, NAND2A, NAND2B, NAND3, NOR2,
NOR3, NOR4, AND2, AND3, AND4, OR2, OR3, OR4,
AOI21, AOI22, OAI21, OAI22.
 SPICE3f5 – simulate delay and leakage.
 MAGIC – to implement layout of H/L variants
Leakage Comparison
(HL / MTCMOS / Regular)
Leakage: HL,MTCMOS vs Regular
Leakage: HL vs MTCMOS
 At cell level, HL and MTCMOS leakage are
comparably low
Circuit Leakage
(Estimate vs SPICE)
 At circuit level, HL leakage is precisely estimable
This is a key contribution
 MTCMOS leakage is very unpredictable (due to
floating nodes in standby)
Circuit Leakage
(HL /MTCMOS)
Design mapped for minimum area
Design mapped for minimum delay
 Note the large circuit leakage range for MTCMOS
 Circuit leakage (HL) is a single deterministic value
 Circuit leakage (HL) smaller than worst case
MTCMOS circuit leakage.
Circuit Delay, Area
Comparison
 Delay:
 Performed “Exact Timing Analysis” to obtain largest
sensitizable delay for circuit.
 Area:
 Place / Route using CADENCE Silicon Ensemble.
 Used 4 routing layers.
 MTCMOS: header and footer device areas added to
regular layout area.
 Tested on 24 circuits from MCNC91 benchmark
suite.
Delay comparison
 Circuits mapped for
minimum delay (SIS)
 Similar results if
circuits mapped for
minimum area (see
paper)
 HL delay less than
MTCMOS delay
Only 1 transition
slower in HL (both
in MTCMOS)
Area Comparison (area mapped)
Conclusions
 Advantages:
 Internal nodes of a gate never float.
 Leakage precisely estimable, unlike MTCMOS
 Delay increase only for one transition.
 We use only one supply gating device.
 MTCMOS requires un-gated supply lines for memory elements.
 We do not need separate supply lines
 We use flip-flop design of Mutoh et. al.
 MTCMOS & HL leakage dramatically lower than regular designs
 HL leakage lower than worst case MTCMOS leakage.
 HL cell layout easily done
 Header, footer regions free for over-the cell routing.
 Disadvantages:
 Determination of optimal primary input vector for minimal leakage
is a complex problem.
 Can be solved using an ADD framework.
Thank you!