Transcript Mesh Currents - Texas A&M University

How to Detect Redundancy
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1. Sort according to
slack Q
2. Scan in decreasing
order of Q
3. Delete if C is not
decreasing
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More on Gate Sizing
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If we increase the gate width
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Driving resistance decreases, therefore the
time to charge and discharge downstream
load decreases
Input capacitance increases, therefore the
time to charge and discharge for the
previous stage increases
Need to consider overall tradeoff
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Wire Sizing
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The metal wire can also be sized
Cell
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Cell
The wider the wire, the less the
resistance, the greater the capacitance
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Power Dissipation of CMOS
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Static dissipation
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Sub-threshold leakage from source to drain
Reverse bias leakage from diffusion to substrate
Gate leakage from gate to drain
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Leakage Power
Static power
Ps=(supply voltage)*(leakage current)
 As the technology shrinks feature size,
static power increases dramatically
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Gate length decreases
Gate oxide thickness decreases
Gate count increases
Leakage current increases
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Dynamic Power
Charging and discharging Cload
Pd=Cload (Vdd)2 f +Psc
where f is frequency of signal switching
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Cload
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Dynamic Power II
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Short circuit current Isc
Psc=2*f*Imean*Vdd
vdd-vtn
vtn
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Power Minimization
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Transistor sizing
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Interconnect optimization
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Smaller the transistor, less the dynamic and static
power
Make wire shorter and thinner, thereby reducing
Cload
Reduce power supply voltage, but this also
slows down the circuit
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Use dual supply voltage Vhigh and Vlow, Vhigh for
time critical paths, and Vlow for other paths
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Power Optimization
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Increase threshold voltage to reduce
leakage, but this also increases delay
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Dual threshold voltage, low threshold for
time critical paths, high threshold for other
paths
More advanced techniques
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Logic synthesis to reduce switching activity
Sleep state, power gating, clock gating,
glitch reduction, …
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Power and Ground
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As the chip size increases, IR drop due
to sudden current change causes noise
and error
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Coordinated dynamic power usage may
cause Vdd charge in a region
If Vdd changes, delay may increase or
decrease
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Power/Ground Analysis
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Solve a differential equation of RCL
circuit to see if any part has “power
starvation”
G*x(t) + C*x’(t) = h(t)
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