Transcript ELEN 468 Advanced Logic Design

ELEN 468
Advanced Logic Design
Lecture 23
Testing
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Verification vs. Testing
Verifies correctness of
design
Performed by
simulation, hardware
emulation, or formal
methods
Performed prior to
manufacturing
Verifies correctness of
manufactured hardware
Two-part process:
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
1. Test generation: software
process executed once during
design
2. Test application: electrical
tests applied to hardware
Test application performed
on every manufactured
device
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Why Do We Need Testing?
Properly designed chip may fail in field
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Transient failures – under heating, radiation …
Intermittent failures – random, finite duration
Permanent failures
Manufacturing defects
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Wafer defects
Contaminated atmosphere in clean room, dust …
Impure processing gasses, water, chemicals …
Photomask misalignment
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Testing Levels and Implied Cost
Wafer: 0.01 – 0.1
Packaged-chip: 0.1 – 1
Board: 1 – 10
System: 10 – 100
Field: 100 – 1000
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Types of Defects
Wire shorts
Discontinuous wires, may due to stress
or peeling
High resistance vias
Gate to source/drain junction short
Threshold voltage change
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Fault Models
Why model faults?
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I/O function tests inadequate, real defects
too numerous and often not analyzable
A fault model
 Identifies targets for testing
 Makes analysis possible
Common fault models
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Transistor open and short faults
Single stuck-at faults
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Single Stuck-at Fault
Three properties define a single stuck-at fault
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Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and 24 single
Faulty circuit value
stuck-at faults
c
1
0
a
d
b
e
Good circuit value
j
s-a-0
g
1
0(1)
1(0)
h
i
z
1
k
f
Test vector for h s-a-0 fault
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Fault Equivalence and Collapsing
Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also detect
f2
Fault collapsing: All single faults of a logic
circuit can be divided into disjoint equivalence
subsets, where all faults in a subset are
mutually equivalent.
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Equivalence Rules
sa0 sa1
sa0
sa0
sa1
sa1
sa0 sa1
AND
sa0 sa1
sa0 sa1
OR
sa0 sa1
sa0 sa1
sa0
sa1
sa0 sa1
NAND
sa0 sa1
WIRE
sa0 sa1
sa0 sa1
NOR
sa0 sa1
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NOT
sa0 sa1
sa0
sa1
sa1
sa0
sa0
sa1
sa0
FANOUT sa1
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Checkpoints
Primary inputs and fanout branches of a combinational
circuit are called checkpoints
Checkpoint theorem: A test set that detects all single
(multiple) stuck-at faults on all checkpoints of a
combinational circuit, also detects all single (multiple)
stuck-at faults in that circuit.
Total fault sites = 16
Checkpoints ( ) = 10
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Transistor (Switch) Faults
MOS transistor is considered an ideal switch
and two types of faults are modeled:
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Stuck-open -- a single transistor is permanently
stuck in the open state
Stuck-short -- a single transistor is permanently
shorted irrespective of its gate voltage
Detection of a stuck-open fault requires two
vectors
Detection of a stuck-short fault requires the
measurement of quiescent current (IDDQ)
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Stuck-Open Example
Vector 1: test for A s-a-0
(Initialization vector)
Vector 2: (test for A s-a-1)
PMOS
1
0
VDD
A two-vector stuck-open test
can be constructed by
ordering two stuck-at tests
A
Stuck-open
0
0
B
C
0
1(Z)
Good circuit states
NMOS
Faulty circuit states
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Stuck-Short Example
Test vector for A s-a-0
VDD
1
0
A
B
Stuck-short
IDDQ path in faulty circuit
Good circuit state
C
0 (X)
Faulty circuit state
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Testing Techniques
IDDQ test – detect short circuit current
Test pattern generation and verify
output
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Test Pattern for Stuck-At Faults
a
b
c
Ygood = a●b●c
No need to enumerate
all input combinations
to detect a fault
a SA1
b
c
Ya-SA1 = b●c
Test pattern: {a,b,c} = 011
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Path Justification and Sensitization
Justification
‘1’
Test SA0
‘1’
Sensitization
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Automatic Test Pattern
Generation (ATPG)
Functional ATPG – generate complete set of tests for circuit inputoutput combinations
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129 inputs, 65 outputs:
2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
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Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
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No redundant adder hardware, 64 bit slices
Each with 27 faults (using fault equivalence)
At most 64 x 27 = 1728 faults (tests)
Takes 0.000001728 s on 1 GHz ATE
Designer gives small set of functional tests – augment with
structural tests to boost coverage to 98+ %
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D-Logic
Inverter
D
In
Out
0
1
0 in good
1 in fault
1
0
X
X
X – don’t care
D
D’
D’
D

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1 in good
0 in fault
D’
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
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D-Algorithm
‘1’
Monitor output
in D logic
‘1’
Test SA0
= trace back input
to enable D
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Algorithm Speedups
Algorithm
Est. speedup over D-ALG
(normalized to D-ALG time)
D-ALG
1
PODEM
7
FAN
23
TOPS
292
SOCRATES
1574
ATPG System
Waicukauski et al. 2189
ATPG System
EST
8765
ATPG System
TRAN
3005
ATPG System
Recursive learning 485
Tafertshofer et al. 25057
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Year
1966
1981
1983
1987
1988
1990
1991
1993
1995
1997
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Fault Simulation
Fault simulation Problem
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Given
 A circuit
 A sequence of test vectors
 A fault model

Determine
 Fault coverage - fraction (or percentage) of modeled
faults detected by test vectors
 Set of undetected faults
Motivation
 Determine test quality and in turn product quality
 Find undetected fault targets to improve tests
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Fault Coverage and Defect Level
W = 1 – Y(1-T)
W: probability of shipping a defective
part
Y: manufacturing yield
T: fault coverage
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Fault Simulator in a VLSI Design Process
Modeled
fault list
Verified design
netlist
Verification
input stimuli
Fault simulator
Test vectors
Remove
tested faults
Fault
Low
coverage
?
Adequate
Stop
Test
compactor
Test
generator
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Delete
vectors
Add vectors
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Fault Simulation Scenario
Mostly single stuck-at faults
Sometimes stuck-open, transition, and path-delay faults
Equivalence fault collapsing of single stuck-at faults
Fault-dropping -- a fault once detected is dropped from
consideration as more vectors are simulated; faultdropping may be suppressed for diagnosis
Fault sampling -- a random sample of faults is simulated
when the circuit is large
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Fault Simulation Algorithms
Serial
Parallel
Concurrent
Probabilistic
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Serial Algorithm
Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each fault:

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Modify netlist by injecting one fault
Simulate modified netlist, vector by vector, comparing
responses with saved responses
If response differs, report fault detection and suspend
simulation of remaining vectors
Advantages:
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Easy to implement, less memory
Most faults, including analog faults, can be simulated
Disadvantage:
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Much repeated computation, CPU time prohibitive for VLSI
circuits
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Parallel Fault Simulation
Best with two-states (0,1)
Exploits inherent bit-parallelism of logic
operations on computer words
Multi-pass simulation: each pass
simulates w-1 new faults, where w is
the machine word length
Speed up over serial method ~ w-1
Not suitable for circuits with timingcritical and non-Boolean logic
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Parallel Fault Simulation Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
1
a
1
b
1
1
1
1
1
1
c
0
1
0
c s-a-0 detected
1
e
1
s-a-0
0
d
0
f
0
1
g
0
s-a-1
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0
0
1
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Concurrent Fault Simulation
Event-driven simulation of fault-free circuit
Only note those parts of the faulty circuit that differ in
signal states from the fault-free circuit
A list per gate containing copies of the gate from all
faulty circuits in which this gate differs
List element contains fault ID, gate input and output
values
Faster than parallel simulation
Uses most memory
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Concurrent Fault Simulation Example
0
0
1
a
1
b
1
1
c
d
1
1
c0
b0
a0
1 0
1
0
0
1
0
e0
0
0 1
d0
0 1
0
1
1
e
1
0
f
0
1
1
0
0
b0
1
a0
0
0
f1
1
1
1 1
0
0
g
0
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g
b0
0
1
0
1
1
1
f1
c0
0
0
e0
0
1
1
1
d0
30
0
Probabilistic Fault Simulation
Identify test vectors with high toggle
coverage
Use them as basis for test vectors
Correlation: toggle coverage  fault
coverage
Toggle tests are simpler
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Fault Sampling
A randomly selected subset (sample) of faults
is simulated
Measured coverage in the sample is used to
estimate fault coverage in the entire circuit.
Advantage: saving in computing resources
(CPU time and memory)
Disadvantage: limited data on undetected
faults - hard to identify location of coverage
problems
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Delay Fault Testing
Half open circuit
Half short circuit
Functionality is not affected
Timing performance is degraded
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