Transcript Hierarchical Design Method

ELEN 468
Advanced Logic Design
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Introduction
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Very Large Scale Integration (VLSI)
Millions of gates integrated on one
silicon chip
 Moore’s law
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Computer-Aided Design (CAD)
 Electronic Design Automation (EDA)
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Using CAD software to design VLSI
circuits.
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Alternative Technologies
Market volume
to amortize,
time to prototype
Full-custom
ICs
Standard
cells
FPGAs
NRE cost,
process complexity
PLDs
density, speed
complexity
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Hierarchical Design
Chip
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Modules
A chip contains many modules
A module may contain other
modules
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Primitives
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no recursion
A module contains primitives
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Design Methods
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Design Entry

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Schematic
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Design data representation
Behavior, RTL, Gate-Transistor Schematics
Draw your design with gates/transistors/lines
For high-performance blocks
Hardware Description Language
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Describe your design with Verilog/VHDL
Just like writing a program
No need to worry about structure
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Schematic Tools
a
b
sum
Add_half
c_out
Block Diagram
a
b
sum
c_out_bar
c_out
Schematic
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Verilog Code
Module Name
Module Ports
module Add_half (sum, c_out, a, b);
input
a,b;
Declaration of Port Modes
output sum, c_out;
wire
c_out_bar;
Declaration of Internal Signal
xor (sum, a, b);
nand (c_out_bar, a, b);
not (c_out, c_out_bar);
endmodule
Instantiation of Primitive Gates
Note: All bold-faced items are Verilog keywords.
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