Transcript Mesh Currents - Texas A&M University

Design Margining
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Uncertain factors
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Temperature
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Supply voltage
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Ids decreases with temperature T-1.5
Commercially parts: 0°C to 70°C
Industrial parts: -40°C to 85°C
Military parts: -55°C to 125°C
Compensation circuits
Normally allow 10% or more
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Process Variation
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Device characteristics follow normal
distribution N(a, )
2
3
Device char within
3 is reported as
variation
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1 =68.26%
2 =95.44%
3 =99.74%
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Process Variation
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Device
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Gate length
Oxide thickness
Doping density
Interconnect
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Metal width, metal thickness
Inter-layer-dielectric thickness
Via resistance
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Impact of Process Variation
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Delay variation wafer-to-wafer, chip-tochip, region-to-region, or random
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Delay Fault
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Path delay fault
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Path delay is d
Process variation causes extra delay Δ
If d +Δ>Tcycle, then there is a delay fault
From PIs
or FFs
To POs
or FFs
output
outputwithout
with
variation
P1
P2
P2
Combinational Circuit
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P1
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Tcycle
5
Design Corners
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Imaginary box that surrounds the
guaranteed performance
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For example, when all devices on one path
has longest gate length, while all devices
on another path has shortest gate length
Rarely happen, but can be a problem
Verification and testing
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Reliability
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Device failure/degradation
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Hot electron effect
Electromigration
Oxide failure
Transistor degradation
Accelerated life testing
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Over-voltage, over-temperature
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