Transcript Limitations of Silicon Technology

Limitations of Digital
Computation
William Trapanese
Richard Wong
Fundamental Limit
Irreversible Logic Device
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First developed by John von Neumann over 50 years
ago and discussed in depth by Rolf Landauer in 1961
Entropy caused by changing states defined by Boltzmann
Principle that:
S = kB ln Ω
Where S = entropy and Ω is number of states
The energy required to overcome this entropy is:
ΔE = T ΔS
E = T kB ln Ω
Since digital logic is binary (Ω = 2) and the energy needed to
change a bit is:
E = kBT ln 2
Fundamental Limit
From this equation known as the von
Neumann – Landauer expression
limits of other properties arise
Ebit ≥ kBT ln 2 = .017 eV.
Use the uncertainity relations to
determine the minimum limits of the
size, density, power and speed of a
digital switching device?
Fundamental Limit
Δx Δp ≥ ħ
ΔE Δt ≥ ħ
xmin = ħ / Δp = ħ / (2 me Ebit).5 = 1.5nm
Where xmin is the minimum size of a switch
nmax = 1 / x 2 = 4.7 x 1013 devices / cm2
Where nmax is the maximum density of switches
tmin = ħ / ΔE = .04 ps
Where tmin is the minimum switching time
Speed = 1 / tmin = 1/.04 = 2.5 x 1013 hz
P = (nmax Ebit) / tmin = 3.7 x 106 W / cm2
Fundamental Limit
The Fundamental Limit Depends on using
mobile electron carriers to change states and
irreversible logic.
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Possible Fixes
Using Reversible Computing Logic
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Only represents minor gains of about 1-2 orders of magnitude
Using New Logic Alternatives
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Spintronics
Phase Chase Logic Devices
Interference devices
Optical Switches
Silicon Transistors
The last 40 years of silicon transistor technology has been achieved
with more or less the same techniques
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Metal-Oxide Semiconductor (MOS) Transistors
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Complimentary MOS (CMOS) circuits to design logic gates
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Materials: Si, SiO2, Al, Si3N4, TiSi2, Tin, W
Moore’s Law
Hi.
A new generation of technology is produced
every 2-3 years
Each new generation has:
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Twice the number of transistors
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Increased performance by 40%
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Four times the memory capacity
Moore’s Law
Increased number of transistors: where does it come from?
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Shrinking lithography dimensions (scaling)
Increase in chip area (cheating!)
“Cleverness” in design
With practical limits on chip area and the general unpredictability of
“cleverness,” scaling is the most important aspect of Moore’s Law
It is estimated that current technology will progress for another 1015 years before a new “breakthrough” is required
Limits of Scaling
Physical Gate Oxide
Thickness
Max Silicide/Si Contact
Resistivity
Source/Drain Extension
Sheet Resistance
S/D Extension Junction
Depth
Oxide Gate Thickness
Present Day
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SiO2 gate oxide
Has a low k
Makes near perfect
electrical interface with
Si
Effectively used up to
1.2nm thickness
Oxide Gate Thickness
Problems
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Although most properties of
the device have been
scaled at similar rates the
gate voltage has not. To
compensate for this, the
electric field across the
capacitor increases.
At about 1nm, the
thickness and large electric
field causes a large
leakage current do to
electron tunneling
Oxide Gate Thickness
Possible Solutions
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Strained Silicon
Used today in 90nm
technology
Allows greater mobility in
channel thus lowering the
leakage current
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High k dielectric
High k allows for larger
thickness while keeping
the same capacitance
Difficult to apply to silicon
base without increasing
scattering in channel
Shallow Junctions
In MOSFET technology,
the current drive limited
by the channel resistance
As MOSFETS get smaller
parasitic resistances are
no longer comparatively
small
To reduce these
resistances doping is
increased
Doping is only feasible till
electrical solubility limits
are reached
Minimum Feature Size (nm)
Isolated Gate Length (nm)
300
120
250
100
200
80
150
60
100
40
50
20
0
0
1997
1999
2002
2005
2008
2011
2014
1997
1999
2002
Year
2005
2008
2011
2014
Year
Equivalent Physical Gate
Dielectric Constant of DRAM Capacitor
6
1600
1400
5
1200
4
1000
3
800
600
2
400
1
200
0
0
1997
1999
2002
2005
Year
2008
2011
2014
1997
1999
2002
2005
Year
2008
2011
2014
Wire Restrictions
While not directly related to silicon technology, wires represent a
fundamental problem in miniaturization of circuits
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As transistors continue to shrink, wires and interconnect do not shrink at
a similar pace
However, more and more wiring is needed to connect the increased
number of transistors
Getting around Wire Limits
Use fewer wires!
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Integrated circuits reduces the need for wiring
Decreasing width of wiring
Layering wires on top of each other
Problems with Decreasing Width
Increases resistance per unit length
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Smaller cross-sectional area means increased resistance per unit length
Capacitance inversely increased, leading to constant RC times
As circuit speed increases, this leads to transmission delays limited by
RC times rather than velocity of Electromagnetic waves
Problem with Longer Wiring
Requires layering to separate each trace
Leads to higher production costs
Result: Production limits are sometimes restricted by monetary
barriers, not technological limitations
Problems with Current Density
Current density increase as cross-sectional area of the wire
decreases
Current density is limited by electromigration, the movement of
atoms by electric currents
Corrected, in part, by copper wiring
Open Circuit Failure
Short Circuit Failure
Current Density
A numerical analysis:
Electron density of copper
Fermi speed, Ef = 7 eV
Conductivity of copper at 20°C
Mean free path of an electron
Resistance, given diameter 1mm and length
1m
Current density, given 1 volt
Drift velocity
More reasonable: 3A current yields 382 A/m^2 and a drift velocity of 0.00028 m/s
“Wire-Limited Chip” Concept
Assumptions: the area needed for wiring dominates the area of the
chip
Each component has area a
The component separation is a^0.5
Average length of the wire channels that must provided per
component is ma^0.5, where m is the length in component pitches
needed to run the wire
Minimum distance between wires is W
K is the number of layers
Ka = m (a)^0.5 W
A = (mW/K)^2