Transcript Lecture 5

ELEC 516 VLSI System Design and
Design Automation Spring 2010
Lecture 5: Flip-Flop/Latch
Design
Reading Assignment:
Rabaey: Chapter 7
Note: some of the figures in this slide set are adapted from the slide set
of “ Digital Integrated Circuits” by Rabaey et. al., Copyright 2002
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Motivations:
Why do we need sequential circuits?
• Need memory
• Pipeline the system so that new
operations start before the old ones
complete.
• Add registers to keep operations
separate.
• Convert parallel operations to a
sequence of serial operations (faster
operations per cycle/ smaller).
• Need to process a sequence of
inputs and want to reuse the same
hardware (Finite State Machine)
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Sequential Logic
FF s
f
LOGIC
Out
tp,comb
In
Memory
Element:
2 storage mechanisms
Stores a value as
•positive feedback
controlled by clock.
•charge-based
May have load signal, etc
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Memory Elements - Latches and flip-flops
• A generic memory element has an internal memory and
some circuitry to control access to the internal memory.
which is controlled by the clock input.
• Memory element differ in many key respect:
– exactly what form of clock signal causes the input data
value to be read;
– how the behavior of data around the read signal from clock
affects the stored value;
– when the stored value is presented to the output;
– whether there is a combinational path from the input to the
output.
• 2 types of memory: latches and edge-triggered flip flop
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– latches - transparent while the internal memory is being set
from the data input
– edge-triggered flip-flops (or register) - not transparent,
reading the input value and changing the flip-flop’s output
are two separate events.
ELEC516/10 Lecture 5
Simple Circuit with Feedback
• One inverter with feedback
– Self-oscillation, 2 gate delays for one period"1"
– Odd-number of inverters with feedback
• self-oscillation of 2x gate delays of one path
“0?"
• Two inverters with feedback
– Memory element (or states)
– Basis for commercial static RAM designs
– Read-only, but has no write function
"1"
"0"
• Memory with read/write capability
– Selectively break the feedback path by transmission
gates to load new value into the cell
– A can be written to Z when LD = 1
LD
• Write SW On & Feedback SW Off
LD’
LD’
– Z holds the value when LD = 0
• Write SW Off & Feedback SW On A
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Z
LD
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Latch versus Register

6
Latch
stores data when
clock is low
•
Register
stores data when
clock rises
D Q
D Q
Clk
Clk
Clk
Clk
D
D
Q
Q
ELEC516/10 Lecture 5
Let’s build a latch

Latches are multiplexers controlled by a clock:

When CLK is high data will pass through otherwise the data is saved or
kept unchanged feedback from output to input
Can be realized using
transmission gates
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Dynamic latch
Stores charge on inverter gate capacitance:




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Uses complementary transmission gate to ensure that storage
node is always strongly driven.
Latch is transparent when transmission gate is closed.
Storage capacitance comes primarily from inverter gate
capacitance.
Setup and hold times determined by transmission gate—must
ensure that value stored on transmission gate is solid.
ELEC516/10 Lecture 5
Dynamic latch- Stored charge leakage
• Stored charge leaks away due to reverse-bias
leakage current.
• Stored value is good for about 1 ms.
• Value must be rewritten to be valid.
• If not loaded every cycle, must ensure that latch is
loaded often enough to keep data valid.
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Non-dynamic latches
• Must use feedback to restore value.
• Some latches are static on one phase (pseudo-static)—load on
one phase, activate feedback on other phase.
• Example - Recirculating latch: Static on one phase:
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Latch-Based Design
• N latch is transparent
when f = 0
• P latch is transparent
when f = 1
f
N
Latch
Logic
P
Latch
Logic
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Positive Feedback: Bi-Stability
Vo1 =Vi2
Vi1
Vo1
Vi2 = Vo1
Vo2
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Vi2 = Vo1
• The circuit presents only
three operation points
• When the gain of the inverter
in the transient region is
larger than 1, A and B are the
only stable operation points &
C is a metastable operation
point.
Vi1
Vo2
A
C
B
Vi1 = Vo2
ELEC516/10 Lecture 5
Meta-Stability
Vi2 = Vo1
Vi2 = Vo1
Gain should be larger than 1 in the transition region
B
C

Vi1 = Vo2

Vi1 = Vo2
• C is an instable operating point. Every deviation (even small) causes
the operation to run away (because of high gain).
• A and B are very stable operation points, the loop gain is much
smaller than unity, eve a large deviation will not cause deviation from
these operation points.
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Flip states in Bistable Circuit
• Two different approaches:
– Cutting the feedback loop
• Open the loop and write data
• Multiplexer based
• Q = Clk’.Q + Clk.In
– Overpowering the feedback loop
• Applying a trigger signal at the input of the flipflop to overpower the stored value to a new
value
• Careful sizing of the transistors in the
feedback loop and the input is necessary
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Writing into a Static Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK
Q
CLK
D
D
CLK
D
CLK
Converting into a MUX
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Forcing the state
(can implement as NMOS-only)
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Other styles
Small and lower clock load
but sizing problems
Very good style
(Skew considerations)
Fast and energy efficient
Presents the lowest
clock load
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Mux-Based Latch
CLK
Q
CLK
D
CLK
• Positive level latch. When the D path is ON, the feedback is cut-off
• No sizing issues for correct operation.
• The number of transistors that the clock drives is an issue (clock has
an activity factor of 1: CLK Load of four transistors.
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Mux-Based Latch
CLK
QM
CLK
QM
CLK
CLK
NMOS only
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Non-overlapping clocks
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DFF Implementation (falling edge
triggered)
Master/Slave latch arrangement
D
D Q
Ds
G Q’
G Q’
Cs
C
D
C
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Q
D Q
Q
Q’
Master D
latch
Slave D
latch
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DFF Internal Operation
D
C
Master
sampling
Ds
Cs
Master
sampling
Xfer to
Slave
Xfer to
Slave
Q
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Flip-Flop: Timing Definitions
f
t
tsetup
thold
In
DATA
STABLE
Out
t
tpFF
DATA
STABLE
t
Setup
time: time before clock during which data input must be stable.
Hold time: time after clock event for which data input must remain
stable.
Clock-to-Q delay = TPFF
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Clk-Q Delay
2.5
Volts
CLK
1.5
0.5
2 0.5
0
22
D
tc 2
q(lh)
tc 2
q(hl)
Q
0.5
1
1.5
time, nsec
2
2.5
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The setup time race
• Setup represents the race
for new data to propagate
around the feedback loop
before clock closed the
input gate.
• If data arrives too close to
clock edge, it will not set up
the feedback loop before
clock closed the input TG
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The hold time race
• Hold time represents the
race for clock to close the
input gate before next
cycle’s data disturbs the
stored value
• If data changes too soon
after the clock edge, clock
might not had time to
switch off the input gate
and new data will corrupt
feedback loop
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Setup Time
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Maximum Clock Frequency
FF’s
f
Also:
tcdreg + tcdlogic > thold
tcd: contamination delay
= minimum delay
LOGIC
tp,comb
tclk-Q + tp,comb + tsetup = T
Modern high performance systems are characterized by low logic depth
The register’s delay becomes very important as the registers because it
accounts for both the setup and propagation delay.
DEC Alpha up has a max logic depth of 12 gates, &15% of the delay
corresponds to the register overhead.
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Reduced Clock Load Master-Slave Register
Eliminate the feedback transmission gate.
CLK
D
T1
CLK
CLK
I1
I2
T2
CLK
I3
Q
I4
Possible problem: reverse conduction
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Clock Overlap Problem
X
CLK
CLK
Q
D
A
B
(a) Schematic diagram
CLK
CLK
Potential problems:
1. Race condition: data at the
output change at the rising
edge of the clock
2. Node A can be driven by both
D and B when clock overlap
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CLK
CLK
(b) Overlapping clock pairs
Variations in the routing wires
Used to route CLK & CLK’
Variations on the load
Inverter’s delay
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2 phase Non-overlapping clock DFF
f
f
D
In
f
f
f
f
tf12
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Two-phase non-overlapping clocks
ELEC516/10 Lecture 5
6 Transistor CMOS SR-Flip Flop
VDD
M2
f
f
M4
Q
S
Q
R
M5
M1
30
M3
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Dynamic Latches and registers
• Disadvantage of static FF - complexity, larger size
• The requirement that the memory should hold state for extended
periods of time can be relaxed in computational structure
• Dynamic - use the charge stored in capacitance to eliminate the use of
inverter pair to latch data: Pseudo-static latch (Charge-Based Storage)
Clk
Clk’
A
B
D
Clk’
Q
Clk
• Clk=1: The input data is sampled on storage node A, during this time
the slave is on hold mode, node B at high impedance.
• On the falling edge of the clock, T2 turns ON and the value sampled on
A propagates to the output.
• Setup time is the delay of the transmission gate
• Hold time is zero since the TG is turned off on the clock edge.
• Tc2q= delay of two inverters and a transmission gate.
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Making a Dynamic Latch Pseudo-Static
• Fully dynamic circuit presents a number of drawbacks:
– Capacitive coupling can inject significant noise to the internal
storage node.
– Leakage current: Most modern processors require that the clock
can be slowed down or completely halted to conserve power in low
activity periods
CLK
D
D
CLK
• Most of these problems can be addressed by adding a weak
feedback inverter  Pseudo-Static Latch
– Slight cost in delay and silicon area.
– Improves noise immunity significantly
– Dynamic latches should be made Pseudo-Static, keep for very
special cases of highly controlled environment (full-custom, high
performance data path design)
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Impact of non-overlapping clocks
Clk
Clk
A
D
B
T1
T2
Clk’
Clk
Q
clk
• During the (0,0) overlap,
clk
PMOS of T1 and PMOS of
T2 are ON, creating a direct
(0,0)
(1,1)
path from D to Q.
Overlap Overlap
• The same problem appears
Overlapping Clocks Can Cause during the (1,1) overlap.
Race Conditions
Undefined Signals
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Flip-flop insensitive to clock overlap
f
VDD
VDD
M2
M6
M4
In
f
M3
X
CL1
f
f
M1
M8
M7
D
CL2
M5
f-section
f-section
C2MOS LATCH
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C2MOS avoids Race Conditions
VDD
VDD
VDD
VDD
M2
M6
M2
M6
0
X
In
1
M3
M1
D
1
M4
X
In
0
M8
D
M7
M5
(a) (1-1) overlap
M1
M5
(b) (0-0) overlap
During the (0,0) overlap, new data sampled on the falling edge of the clock
will not appear at D output.
Same remark applied during the (1,1) overlap.
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Operation of the C2MOS latch
• When f = 1, M3 and M4 are on, the 1st section is in
the evaluation mode and the second section is in a
hold mode (high impedance). M7 and M8 are off,
decoupling the output from the input. The input D
retains its previous value stored on the output
capacitance.
• When f = 0, the first section is in hold mode and the
second section is in evaluation mode, the value
stored in CL1 propagates to the output node.
• A C2MOS register with (f - f ) clocking is insensitive
to overlap, as long as rise and fall times of the clock
edges are sufficiently small.
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Dual Edge registers
• Dual Edge registers are very interesting as they permit to
run the Clock 2 times slower  lower power on the clock
node.
D
f
N1
X
f
f
f
N2
Q
f
N1
f
Y
f
f
N2
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Pipelined Logic using C2MOS
VDD
In
VDD
f
f
NORA CMOSVDD
f
f
F
C1
G
f
C2
f
Out
C3
What are the constraints on F and G?
No-race rule: A C2MOS-based pipelined circuit is race-free
as long as the logic function F (static logic) between the
latches are non-inverting
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Example
VDD
VDD
VDD
f
f
f
f
1
Number of a static inversions should be even
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Doubled C2MOS Latches-True singlephase clock register
VDD
VDD
VDD
VDD
Out
In
f
f
Doubled n-C2 MOS latch
(transparent when CLK= 1)
In
f
f
Out
Doubled p-C2 MOS latch
(transparent when CLK= 0)
+ Requires a single clock to build a positive & negative clock
- Can suffer from charge sharing & noise pbs when clk low.
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TSPC - True Single Phase Clock Logic
VDD
VDD
VDD
VDD
PUN
In
f
f
Static
Logic
f
f
Out
PDN
Including logic into
the latch
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Inserting logic between
latches
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Example of Including Logic in TSPC
V DD
In 1
V DD
In 2
Q
CLK
CLK
In 1
In 2
AND latch
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• Embedding logic into the
latch reduces the delay
overhead of the latch.
• This approach of
embedding logic into the
latch was extensively used
in many high performance
microprocessors
including EV4 DEC Alpha.
ELEC516/10 Lecture 5
Master-Slave Flip-flops
VDD
V DD
f
D
f
VDD
V DD
f
Y
X
V DD
V DD
D
f
D
f
f
D
f
f
(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered
D flip flop
VDD
D
f
V DD
f
V DD
D
(c) Positive edge-triggered D flip-flop
using split-output latches
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Pulse-Triggered Latches
An Alternative Approach
Ways to design an edge-triggered sequential cell:
IDEA: construct a short pulse around the rising (or falling)
edge of the clock. This would be the NEW clock input.
Hold time is equal to the length of the pulse.
Master-Slave
Pulse-Triggered Latch
Latches
L1
L2
L
Data
D Q
D Q
Clk
Clk
Data
Clk
D Q
Clk
Clk
+ Reduced clock load, small number of transistors required.
+ Glitch circuitry can be shared by multiple register.
- increase in verification complexity: Need to make sure the glitch
Is properly generated!!!!!
ELEC516/10 Lecture 5
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Pulsed Latches
VDD
VDD
M3
M6
CLK
Glitch corresponds
to the delay of the
AND + 2 Inv
VDD
Q
D
CLKG
M2
CLKG
M1
MP
M5
CLKG
X
MN
M4
(a) register
(b) glitch generation
CLK
CLKG
(c) glitch clock
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Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
CLK
P1
P3
x
M6
M3
D
M2
M1
Q
P2
CLKD
M5
M4
• When the clock is low: M3 and M6 are off and P1 is ON. Node X is
precharged to VDD, and the output is decoupled from X (Memory).
• CLKD’ is a delayed-inverted version of CLK. On the rising edge of the
clock, M3 and M6 turn ON while M1 and M4 stay ON for a short
period, and hence the latch is transparent and D is sampled. Once
CLKD’ goes low node X is decoupled from D.
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Hybrid Latch-FF Timing
Advantage: Setup time can be negative: Transparency window
Is longer than the delay from input to the output.
D injected after
the clock.
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Pipelining
f
f
a
Out
LOG
b
f
48
a
Out
LOG
b
f
f
f
f
f
ELEC516/10 Lecture 5
Latch-Based Pipeline
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NORA (NO Race) CMOS Modules
VD D
VDD
f
In1
In2
In3
VDD
f
f
PUN
PDN
f
f
(a) f-module
f
Combinational logic
VDD
f
Latch
VDD
VDD
VD D
In 4
f
In 1
In 2
In 3
PDN
Out
f
f
(b) f-module
In4
f block
Logic
f =0
50
Out
f =1
Precharge
Evaluate
Latch
Hold
Evaluate
f block
Latch
Logic
Evaluate
Evaluate
Precharge
Hold
ELEC516/10 Lecture 5
Non-Bistable Sequential Circuits─
Schmitt Trigger
V OH
Vou t
In
Out
•VTC with hysteresis
V OL
•Restores signal slopes
VM–
51
VM+
Vi n
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Noise Suppression using Schmitt
Trigger
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CMOS Schmitt Trigger
VDD
M2
Vin
M4
Vout
X
M1
M3
Moves switching threshold
of the first inverter
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Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0
VM1
1.5
(V)
1.0
X
V
1.5
(V)
1.0
x
V
VM2
0.5
0.0
0.0
k=3
k=2
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
Voltage-transfer characteristics with hysteresis.
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k=1
k=4
0.0
0.0
0.5
1.0
1.5
Vin (V)
2.0
2.5
The effect of varying the ratio of the
PMOS device M4. The width is k* 0.5m m.
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CMOS Schmitt Trigger (2)
VDD
M4
M6
M3
In
Out
M2
X
M5
VDD
M1
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Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
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Transition-Triggered Monostable
In
DELAY
td
57
Out
td
ELEC516/10 Lecture 5
Monostable Trigger (RC-based)
VDD
R
In
A
B
Out
(a) Trigger circuit.
C
In
B
VM
Out
t
t1
58
(b) Waveforms.
t2
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Astable Multivibrators (Oscillators)
0
1
2
N-1
Ring Oscillator
simulated response of 5-stage oscillator
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Voltage Controller Oscillator (VCO)
VD D
VDD
M6
M4
Schmitt Trigger
restores signal slopes
M2
In
M1
Iref
Vcontr
Iref
M3
M5
Current starved inverter
tpH L (nsec)
6
4
2
0.0
0.5
60
1.5
V co ntr (V)
2.5
propagation delay as a function
of control voltage
ELEC516/10 Lecture 5
Differential Delay Element and VCO
V o2
v3
V o1
v1
in 1
in 2
v2
v
4
V ctrl
delay cell
two stage VCO
3.0
2.5
V1 V2 V3 V4
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
2.5
3.5
time (ns)
simulated waveforms of 2-stage VCO
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