Transcript No Slide Title

SEU Hardening Techniques for
Retargetable, Scalable, Sub-Micron
Digital Circuits and Libraries*
M. P. Baze, J. C. Killens, R. A. Paup, W. P. Snapp
Boeing Space and Communications
Seattle, WA
* Work supported by DTRA contract DTRA01-00-C-0046
“Multi-Fab” IC Design Environment
Multi-Fab environments may be –
• Manufacturing design house possessing several processes
– usually with some process similarity
• “Fabless” design house with access to several processes via
-Single manufacturer with several processes
-Third party interface, i.e. MOSIS
-Independent agreements with several manufacturers
7/20/2015
2
“Multi-Fab” Issues
• Advantage of Multi-Fab Environment
Utilization of different fabrication processes as design options
Accomplished by
“Retargeting” designs to different process technologies.
or
“Scaling” designs to smaller rules in same technology.
• Retargetability – Ease of design transfer to different process.
Bulk, EPI, N-Well, P- Well, Twin Tub, SIMOX, SOS, SOI-MESA, Twin
Tub, Single Poly, Dual Poly, # Metal Layers, Resistor Types,
Capacitor Types, Device Models, etc.
• Scalability – Ease with which a design can be scaled down in
feature size, without sacrificing the advantages of scaling.
7/20/2015
3
Retargeting and Scaling Designs
Standard Digital
Cell Functions
Process A
VHDL
Design A (8051)
VHDL
Design B (1773)
VHDL
Design C (BC30)
Library A
Library B
Process B
Library B/2
Process B/2
Targeting / Scaling
7/20/2015
Synthesis
4
Retargeting and Scaling Designs
SEU Hardening
cap.s, filters, redundant, Idrive, etc.
HARD 2
HARD 3
HARD 1
VHDL (H2, H3)
Design B (1773)
VHDL(H1, H3)
Design C (BC30)
A-3
A-1
Process A
A-2
B-1
Process B
VHDL (H1, 2, 3)
Design A (8051)
B-2
B/2-3
Process B/2
7/20/2015
B/2-2
Targeting / Scaling
Synthesis
5
Basic SEU Hardening Options
Three Categories of SEU Hardening Techniques
1. Charge Dissipation
- Consumes power
2. Temporal Filtering
- Reduces speed
3. Spatial Redundancy - Consumes area
• Charge Dissipation & Temporal Filtering - Increase LETT
• Spatial Redundancy – Reduce effective X-section
7/20/2015
6
Charge Dissipation
Increase Transistor Current Drive
“STANDARD”
NAND2
Sink QCOL to prevent “valid” pulse widths
VDD
IN0
OU
T
IN1
where “valid” > register TSH
VSS
transistor IDRIVE > QCOL / Register TSH
• Retargetability
Increases area of
standard cell
library
7/20/2015
VDD
HARDENED
NAND2
•Scalability
Speed – no significant penalty
IN0
OUT
IN1
Area – in proportion to drive
Power – in proportion to drive
VSS
7
Charge Dissipation
Adding Capacitors in Combinational Logic
VDD
1) Keep direct hit from crossing ½ VDD
- Required Cap > 2 x (QCOL / VDD)
+
+
IN0
OUT
IN1
2) Keep input transient from crossing ½ VDD
Required Cap > 2 x IDRIVE x PW / VDD
:
Capacitor
however since PW ~ QCOL / IDRIVE “upstream” , then
- Required Cap > 2 x (QCOL / VDD), independent of global IDRIVE sizing
Set Hardness Cap> 2 x (QCOL / VDD)
Trade power vs speed with global transistor sizing
• Retargetability
Implemented by adding/sizing
cap’s to standard soft library
7/20/2015
• Scalability
Speed, power, area penalties may
negate many advantages of scaling
8
Charge Dissipation / Temporal Filtering
Adding Capacitors in sequential logic
+
+
1) Keep direct hit from crossing ½ VDD
- Required Cap > 2 x (QCOL / VDD)
2) Lengthen TSH - short input transients “invalid”
Register TSH > QCOL / transistor IDRIVE
• Retargetability
Implemented by adding/sizing
cap’s to standard soft library
7/20/2015
Capacitor
• Scalability
Speed, power penalties may negate
many advantages of scaling
9
Temporal Filtering
“Delay-and-Vote”
in
Combinational
logic
Network
Voting
Circuit
delay
delay
out
delay
Total Delay = 2 x Error Pulse Width ~ 2 x (QCOL / IDRIVE )
if IDRIVE = 0.25 mA and QCOL = 0.4 pC then 2 x (QCOL / IDRIVE ) = 3.2 ns
• Retargetability
Architecture implementation.
Delay element redesign for
each process.
7/20/2015
• Scalability
If QCOL does not scale down with
IDRIVE, the required delay increases
10
Spatial Redundancy - TMR
Triple Mode Redundancy (TMR)
Error on OUT requires simultaneous
errors in 2 or more logic networks
• Does not increase LET threshold
Logic Network
INPUTS
• Does reduce effective cross-section by
Logic Network
Voting
Circuit
OUT
Logic Network
geometric probability of multiple node hit
X-sec EFF ~ 1 / (node separation)2
~3X power and area penalty
• Retargetability
Architecture implementation.
Modified structural netlists and/or
cells
7/20/2015
• Scalability
Adequate separation is critical
11
TMR - Node Separation
Triple Redundant Flip/flops
Vdd
D
Q
CLR
Bad Layout Practice
1
CLK
PRE
- “Rail stacking” of
voted F/F’s
2
voter
Q
Vdd
Adjacent redundant
elements
D
Q
CLR
3
CLK
PRE
7/20/2015
12
TMR - Node Separation
Triple Redundant Flip/flops
Vdd
D
CL
R
CL
K
PRE
D
CL
R
CL
K
PRE
D
CL
R
CL
K
PRE
Q
1
2
Q
Q
voter
Q
3
• Acceptable Layout
- “Sequencing” of voted F/F’s
Places redundant elements at greater distance
7/20/2015
13
Internally Redundant Logic
Places redundant nodes in very close proximity - Cell layout critical
“Dual Data Stream”
redundant logic**
Isolated Well
Transistors*
Vdd
PA
Vdd
PB
PA
Pdrive
PC
Pshunt
IN
Nshunt
PC
Pout
P isolation
OUT
Vdd
Nout
NA
N isolation
NC
• Retargetability
NB
Nout
NA
NC
NB
• Scalability
Non-standard library cells.
Transistors often need sizing to
maintain performance.
*Baze, et, al. IEEE NSREC ’00, pg 2609
Pout
Vdd
Ndrive
7/20/2015
PB
Adequate separation is critical
**Wiseman, IEEE Rad. Data Workshop, ’94, pg51
14
Internally Redundant Latch
Cross Coupled (asymmetric)
Redundant state nodes
PMOS
PMOS
BASIC
LATCH
PMOS
PMOS
• Retargetability / Scalability
7/20/2015
Requires custom sizing of six transistors with each new
process to balance the single node SEU response and
achieve adequate hardness
15
Internally Redundant Latch
DICE* - Dual interlocked storage cell
Less sensitive to transistor sizing
Table 2. Single Event Effects Test Results **
**
clock
data
*Calin, et al, IEEE NSREC ’96, pg2877
7/20/2015
**Alexander, et al. GOMAC 2001 Digest of Papers, pg 257
16
Low Power DICE Latch with PRE / CLR
• Low Power – pass gates
PRE
CLK
• Clear
CLKB2
• Preset
Q
CLKB1
• Output buffer
D
CLK
CLKB2
CLK
CLKB1
CLK
CLK
CLK
CLKB2
CLR
CLKB1
7/20/2015
17
DICE Latch Layout Restrictions
PRE
No two same color
transistor blocks may
be paced side by side
CLK
CLKB2
Q
CLKB1
D
CLK
CLK
CLKB1
CLKB2
CLK
CLK
CLK
CLKB2
CLR
CLKB1
7/20/2015
18
DICE Flip/Flop
PRE
CLKB2
CLK
CLK
CLKB1
CLKB2
CLK
D
CLK
Q
CLK
CLKB1
CLKB1
CLKB2
CLK
CLK
CLKB2
CLKB2
CLKB1
CLK
CLK
CLR
CLK
CLKB1
• Retargetability
Transistor sizing and pass gate/ logic
implementations may need to be
traded to optimize speed vs. power
7/20/2015
• Scalability
Single node hardness
insensitive to transistor sizing.
Node separation is critical
19
Flip/Flop Comparisons
• Retargetable / Scalable Flip/Flops in a Single Process
SPEED
(CLK-Q)
(TSH)
Rise – 0.7 mW
Rise – 0.21 ns
Fall – 0.2 mW
Fall – 0.27 ns
Rise – 1.0 mW
Rise – 0.16 ns
Fall – 0.2 mW
Fall – 0.15 ns
Low Power
triplicate-and-vote
Rise – 1.72 mW
Rise – 0.21 ns
Fall – 1.27 mW
Fall – 0.27 ns
DICE
Rise – 1.4 mW
Rise – 0.96 ns
Fall – 1.1 mW
Fall – 0.97 ns
Std Low Power
Increased IDRIVE
7/20/2015
POWER
HARDNESS*
AREA
(e/b-d)
(mm2)
10-8
360
1 node
2x10-9
460
1 node
10-11
1200
2 node
1.6 x10-10
520
2 node
*preliminary estimates for a proposed SOI process, GEO orbit
20
Summary
A number of design options exist for
improving the SEU hardness of digital logic.
However, specific considerations and
restrictions must be observed for each
technique if these techniques are to be applied
over a range of process technologies and
reduced feature size.
7/20/2015
21