Transcript Chapter 6
Chapter 6 (I) Designing Combinational Logic Circuits •Dynamic CMOS Logic V1.0 5/4/2003 1 EE141 Combinational Circuits Revision Chronicle 5/4: Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic 2 EE141 Combinational Circuits Dynamic CMOS In static circuits at every point in time (except when switching), the output is connected to either GND or VDD via a low resistance path. Fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. Requires on n + 2 (n+1 N-type + 1 P-type) transistors 3 EE141 Combinational Circuits Dynamic Gate Clk Clk Mp off Mp on Out In1 In2 In3 Clk CL PDN 1 Out ((AB)+C) A C B Me Clk off Me on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) 5 EE141 Combinational Circuits Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL 6 EE141 Combinational Circuits Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL 7 EE141 Combinational Circuits Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching Higher transition probabilities Extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn Low noise margin (NML) Needs a precharge/evaluate clock 8 EE141 Combinational Circuits Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk Me Evaluate VOut Precharge Leakage sources Dominant component is subthreshold current 9 EE141 Combinational Circuits Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic 10 EE141 Combinational Circuits Issues in Dynamic Design 2: Charge Sharing Clk Mp Out A CL B=0 Clk Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness CA Me CB 11 EE141 Combinational Circuits Charge Sharing Example Clk A A B B B Cc=15fF C C Ca=15fF Out CL=50fF !B Cb=15fF Cd=10fF Clk 12 EE141 Combinational Circuits Charge Sharing VV DD case 1) if V out < VTn DD Clk Mp Mp Out Out CL A CL Ma A Ma X X B =B0= 0 Clk MM b b MM e e Ca C Cb Cb C L VDD = C L Vout t + Ca VDD – V Tn V X or Ca V out = Vout t – V DD = – -------- V DD – V Tn V X CL case 2) if V out > VTn Ca --------------------- Vout = –V DD Ca + CL 13 EE141 Combinational Circuits Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) 14 EE141 Combinational Circuits Issues in Dynamic Design 3: Backgate Coupling Clk Mp A=0 Out1 =1 CL1 Out2 =0 CL2 In B=0 Clk Me Dynamic NAND Static NAND 15 EE141 Combinational Circuits Backgate Coupling Effect 3 2 Out1 1 Clk 0 In Out2 2 Time, ns -1 0 4 6 16 EE141 Combinational Circuits Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and Clk input of the precharge device Clk Mp A CL due to the gate to drain capacitance. The voltage of Out can rise B Clk Out above VDD. Me The fast rising (and falling edges) of the clock couple to Out. 17 EE141 Combinational Circuits Clock Feedthrough Clock feedthrough Clk Out 2.5 In1 In2 1.5 In3 In & Clk 0.5 In4 Clk Out -0.5 0 0.5 Time, ns 1 Clock feedthrough 18 EE141 Combinational Circuits Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) 19 EE141 Combinational Circuits Cascading Dynamic Gates V Clk Mp Clk Mp Out1 Me Clk Out2 In In Clk Clk Me Out1 VTn V Out2 t Only 0 1 transitions allowed at inputs! 20 EE141 Combinational Circuits Domino Logic Clk In1 In2 In3 Clk Mp 11 10 PDN Me Out1 Clk Mp Mkp Out2 00 01 In4 In5 Clk PDN Me 21 EE141 Combinational Circuits Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Ini Inj PDN Ini Inj PDN Like falling dominos! 22 EE141 Combinational Circuits Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort 23 EE141 Combinational Circuits Designing with Domino Logic VDD VDD VDD Clk Mp Clk Mp Out1 Mr Out2 In1 In2 In3 PDN PDN In4 Can be eliminated! Clk Me Clk Me Inputs = 0 during precharge 24 EE141 Combinational Circuits Footless Domino VDD Clk VDD Mp Clk Mp Out1 0 Clk 1 0 Outn 1 0 In2 0 Mp Out2 In1 1 VDD 1 0 In3 1 0 1 Inn 1 0 The first gate in the chain needs a foot switch Precharge is rippling – short-circuit current A solution is to delay the clock for each stage 25 EE141 Combinational Circuits Differential (Dual Rail) Domino off Mp Mkp Clk Out = AB 1 on Mkp 0 Clk Mp 1 A !A 0 Out = AB !B B Clk Me Solves the problem of non-inverting logic 26 EE141 Combinational Circuits np-CMOS Clk In1 In2 In3 Clk Mp 11 10 PDN Me Out1 Clk Me In4 In5 PUN 00 01 Clk Mp Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN 27 EE141 Combinational Circuits NORA Logic Clk In1 In2 In3 Clk Mp 11 10 Out1 PDN Clk Me In4 In5 PUN 00 01 Clk Me to other PDN’s WARNING: Very Sensitive to Noise! EE141 Mp Out2 (to PDN) to other PUN’s 28 Combinational Circuits