Transcript Lecture on Flip Flops

Edge Triggered Flip Flops
(extended slides)
Level-Sensitive Flip-Flop
• Level-sensitive flip-flop (also called a latch)
• Q changes whenever clock is high
CLK
D
Q
CLK
D
Q
Level-Sensitive Flip-Flop
• NMOS transistor often
replaced with
transmission gate
CLK
D
• Transmission gate includes
both NMOS and PMOS
transistors because NMOS
good at passing 0 and PMOS
good at passing 1
CLK
D
CLK
Transmission
Gate
CLK
Q
Q
CLK
6 Transistors
Master-Slave Edge-Triggered Flip-Flop
• Can connect two level-sensitive latches in Master-Slave
configuration to form edge-triggered flip-flop
• Master latch catches value of D at QM when CLK is low
• Slave latch causes Q to change only at rising edge of CLK
D
CLK
CLK
CLK
D
QM
Q
QM
Master
Latch
Slave
Latch
Q
2 x 6 = 12 Transistors
Setup Time & Flip-Flop Progation Delay
• Setup time: D must be stable some setup time before the rising
edge of the clock, e.g. tsetup = 1 ns
• Propagation delay: amount of time after the rising edge of the
clock before Q completely changes, e.g. tFFdelay = 1 ns
tsetup
D
tFFdelay
QM
Master
Latch
CLK
CLK
CLK
D
tsetup
Q
tFFdelay
Slave
Latch
Q
Setup Time & FF Delay
• Suppose tsetup = 1 ns , tFFdelay = 1 ns, and tinv = 1 ns, then clock
period is 4 ns (or 250 MHz)
edge
triggered
D-FF
edge
triggered
D-FF
CLK
CLK
RS-Latch as Cross-Coupled NOR Gates
•
•
•
•
If R = 1, Q resets to 0
If S = 1, Q sets to 1
If RS = 00, no change
RS = 11 is not allowed
because leads to oscillation
R
Q
Q
S
SR
Q
00
No change
01
0
10
1
11
Undefined
Level-Sensitive RS-Latch
• Q only changes when CLK is high (i.e. level-sensitive)
• When CLK is high, behavior same as RS latch
S
S
Q
CLK
Q
CLK
Q
R
Q
R
CLK
SR
Q
0
XX
No change
1
00
No change
1
01
0
1
10
1
1
11
Undefined
Level-Sensitive D-Latch
• Make level-sensitive D-latch from level-sensitive RS-latch by
connecting S = D and R = not D
D
D
Q
Q
CLK
CLK
Q
Q
18 Transistors
• Compared to transistor version
CLK
D
Q
6 Transistors
CLK
JK Flip-Flop from D-Latch
• Same as RS-Latch except it toggles on 11
J
Q
D
Latch
K
Q
CLK
J
Q
JK-FF
CLK
K
CLK
JK
Q
0
XX
No change
1
00
No change
1
01
0
1
10
1
1
11
Toggle
Toggle Flip-Flop from D-Latch
• Toggles stored value if T = 1 when CLK is high
Q
D
Latch
T
CLK
T
Q
T-FF
CLK
CLK
T
Q
0
X
No change
1
0
No change
1
1
Toggle