Transcript Flip-Flops - Educypedia

Flip-Flops
Basic RS Flip-Flop (NAND)
1
0
S (set)
1
1
0
R (reset)
2
(a) Logic diagram
A flip-flop holds 1 "bit".
"Bit" ::= "binary digit."
S R Q Q’
Q
1 0 0 1
1 1 0 1 (after S = 1, R = 0)
0 1 1 0
1 1 1 0 (after S = 0, R = 1)
Q’
0 0 1 1
’
(b) Truth table
Clocked D Flip-Flop
D
3
1
Q
2
Q’
CP
5
4
The present state is held when CP is low.
Clock Pulse Definition
Positive Pulse
Negative Pulse
Positive Negative
Edge
Edge
Negative Positive
Edge
Edge
Edges can also be referred to as leading and trailing.
Master-Slave Flip-Flop
S
Y
S
Master
R
R
Q
S
Slave
Y’
R
CP
MASTER-SLAVE FLIP-FLOP
Q’
Flip-Flop on RT54SX-A
(Not hardened)
Master
Slave
UMC A54SX32A 0.22 m Heavy Ion Test
Device/Date Code = D7766.12 WFR #15
NASA/Goddard Space Flight Center
Brookhaven National Lab
October, 2000
RT54SX-A SEU Performance
10-6
10-7
2
Cross-section (cm /flip-flop)
Flip-Flop String
Flip-Flop String w/ Buffers
Notes:
1. S/N LAN4001
2. Ions = 210 MeV Cl-35, 284 MeV Br-81, 345 MeV I-127
3. Fluence ~ 107 ions/cm2
4. Bias = 4.5, 2.25 VDC
5. Checkerboard pattern
6. Frequency = 1 MHz
7. 200 flip-flops / string
8. Regular CLK Buffer
10-8
10-9
0
10
20
30
LET (MeV-cm2/mg)
40
50
60
RT54SX-S Latch
(SEU Hardened)
AFB
D
ANQ
B
A
A
Y A
A
Y
Y
A
S
A
A
B
B
C
C
A
A
B
B
C
C
A
A
B
B
C
C
Y
BFB
BNQ
B
A
Y B
A
Y
Y
A
B
S
Y
CFB
B
A
G
CNQ
Y
S
A
Y C
A
Y
C
Y
A
Y
Flip-Flop Timing: RT54SX-S
Worst-case Military Conditions, VCCA=2.3, VCCI=3.0V, TJ=125C
-1 Speed Grade
Min
Max
Units
tRCO
Sequential Clock-to-Q
1.0
ns
tCLR
Asynchronous Clear-to-Q
0.9
ns
tPRESET Asynchronous Preset-to-Q
1.0
ns
tSUD
Flip-Flop Data Input Set-Up
0.6
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN Asynchronous Pulse Width
1.8
ns
Metastability - Introduction
• Can occur if the setup, hold time, or clock pulse width of a
flip-flop is not met.
• A problem for asynchronous systems or events.
• Can be a problem in synchronous systems.
• Three possible symptoms:
– Increased CLK -> Q delay.
– Output a non-logic level
– Output switching and then returning to its original state.
• Theoretically, the amount of time a device stays in the
metastable state may be infinite.
• Many designers are not aware of metastability.
Metastability
• In practical circuits, there is sufficient noise to move the
device output of the metastable state and into one of the
two legal ones. This time can not be bound. It is
statistical.
• Factors that affect a flip-flop's metastable "performance"
include the circuit design and the process the device is
fabricated on.
• The resolution time is not linear with increased circuit time
and the MTBF is an exponential function of the available
slack time.
Metastability - Calculation
• MTBF = eK2*t / ( K1 x FCLK x FDATA)
t is the slack time available for settling
K1 and K2 are constants that are characteristic of the flip-flop
Fclock and Fdata are the frequency of the synchronizing clock and
asynchronous data.
• Software is available to automate the calculations with
built-in tables of parameters.
• Not all manufacturers provide data.
Metastability - Sample Data
Sample Metastable Time Data
CX2001 Technology
50 MHz clock, 10 MHz data rate
25
20
log10 (MTBF (years))
15
10
5
0
-5
-10
Note: Each flip-flop has its own K1, K2 parameters.
-15
0
1
2
3
4
5
6
7
8
9
10
Slack Time (ns)
11
12
13
14
15
16
Synchronizer (Bad Circuit)
VCC
Y
D
Q
DFC1B
EVENT
SYSRESET
SYSCLK
CLK
CLR
B AND 2A
Y
A
D
Q
DF1
CLK
Metastable State:
Possible Output from a Flip-flop
CLK
D
Metastable
Q
Metastable State:
Possible Outputs from a Flip-flop
CLK
Q
Q
Q
Correct Output
Parallel Registers
CLOCK
DATA [ 3 : 0 ]
4-Bit Parallel Register
D
DF1
CLK
D
DF1
CLK
D
DF1
CLK
D
DF1
CLK
Q
Q
Q
Q
Q[3:0]
CLOCK
DATA [ 3 : 0 ]
4-Bit Register With Enable
D
DF1
CLK
D
DF1
CLK
D
DF1
CLK
D
DF1
CLK
Q
Q
Q
Q
Q[3:0]
Register Files (Simplified)
Register 2
Q
D
CLK
Register 1
Address - log2(num registers)
D and Q are both sets of lines, with the number of lines
equal to the width of each register. There are often multiple
address ports, as well as additional data ports.
Memory Devices
Magnetic
Core
Memory
Register
Decoder
(AND plane)
Sense wires serve as OR plane.
Semiconductor
Memory
Data
inputs
D0
D1
Word 0
D2
D3
Memory
enable
Read/write
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
BC
Word 1
Address
inputs
Decoder
(AND plane)
BC
Word 2
Word3
OR plane
Data
outputs
Rad-Hard PROM Architecture
A5 - A11
Row Decoders
Memory Array
A0 - A4
Column Decoders
A12 - A14
Section Select
Column Muxing
and
Sense Amps
CE
OE
VPP*
Control Logic
I/O Buffers
No latches in this architecture
DQ0 - 7
W28C64 EEPROM
Simplified Block Diagram
A6-12
A0-5
CE*
WE*
Row
Address
Latches
Row
Address
Decoder
Column
Address
Latches
Column
Address
Decoder
Edge
Detect &
Latches
E2
Memory
Array
64 Byte
Page
Buffer
Timer
Latch Enable
OE*
Control
Latch
I/O Buffer/
Data Polling
Control
Logic
PE
RSTB
CLK
VW
I/O0-7