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CP208 Digital Electronics
Class Lecture 11
May 13, 2009
In This Class
We Will Discuss:
Chapter 11:
Memory and Advanced Digital Circuits
Memory and Advanced
Digital Circuits
3
Introduction
• Chapter 10 was about Combinational logic
circuits – output of which depends on the
present value of the input, that is NO MEMORY
• Memory is very important part of digital systems
• Memory in digital computers allows for storing
programs and data
• Also, it is important for temporary storage of the
output produced by combinational circuit for use
at later time in the operation of a digital system
• Logic circuits that incorporate memory are called
sequential circuits
Introduction
• Sequential circuits have output that
depends not only on the present value of
input but also on the input’s previous
value. Such circuits require a timing
generator for their operation
Introduction
• How Does It Work …
• In first approach application of positive
feedback provides a circuit with two stable
states. Bistable circuit then stores a BIT of
information: One state correspond to
stored 0 and the other to stored 1
• Bistable circuit can remain in either state
indefinitely and hence named as Static
Sequential Circuit
Introduction
• In second approach charge on
capacitor is used to realize memory.
– Charged capacitor corresponds to stored 1
and
– Discharged capacitor corresponds to stored 0.
– Because leakage effects cause capacitor to
discharge, this form requires periodic
recharging of capacitor or Refresh.
• These circuit are named as Dynamic
Sequential Circuit
11.1 Latches and Flip-Flops
• Latch is the Basic Memory Element, we shall
consider a sampling of its application
11.1.1 The Latch
• Latch consists of two Cross-coupled Logic
Inverters
• Inverters form a Positive-feedback Loop
Three Operating Points
A, B, and C.
Two Stable Operating
Points, A and C.
At C: vW = vZ is High,
vX = vY is Low.
At A: Reverse is True.
Now, X and Z are Latch
Out Puts.
In State A: vX is High
(VOH) and vZ is Low (VOL).
In State C: vX is Low
(VOL) and vZ is High
(VOH).
Thus, Latch is Bistable
Ckt having Two
Complementary Outputs
• The Stable State in which Latch Operates
depends on the External Excitation that Forces it
into. The latch then Memorizes this External
Action by Staying in the Acquired State
Indefinitely (Static Memory).
• Latch is capable of Storing One Bit of
Information, e.g., we can designate State A
corresponding to Logic 1. The other
complementary State C would be Logic 0.
• What is the mechanism by which Latch can be
Triggered to Change State?
Latch with a Triggering Mechanism/Circuitry
forms a …
… Flip
– Flop
Simplest Flip-Flop is Set/Reset (SR) FlipFlop…
…NEXT
11.1.2 The SR Flip-Flop
• Simple type of Flip-Flop is Set/Reset (SR)
• It is formed by cross coupling two NOR gates
and thus Incorporates Latch
Second Input of each NOR
Gate Labeled as S and R
serve as Trigger
Outputs Q and Q emphasize
their Complementarity.
Set State (Storing 1): When Q is High and Q is Low.
Reset State (Storing 0): Opposite of Set
Rest or Memory State (when we do not wish to
change state of Flip-Flop) : Both S and R inputs Low
Consider the Case When Flip-Flop is
Storing Logic 0 Q is Low and Q is High.
Since Q is low, Both inputs to G2 will be Low
and its Output will therefore be High.
High Output of G2 is applied to Input of G1,
causing its Output Q to be Low (since R is
Low), satisfying the Original Assumption.
To Set Flip-Flop [To Store Logic 1] Q High and Q Low.
Raise S to Logic-1 Level While Leave R at 0.
Output Q of G2 to 0 or Low.
Two Inputs of G1 will be 0 or Low, causing its
Output Q to be 1 or High.
Now, if S returns to 0 Flip-Flop remains Set.
Raising S to 1 again will make No Change.
To Reset Flip-Flop [To Store Logic 0]
Q Low and Q High.
Raise R to Logic-1 Level While Leave S at 0.
SHOW… The Flip-Flop will be Forced to Reset State and
will remain in This State even after R returns to 0. Raising R
to 1 again will make No Change.
Note that the Trigger Signal Merely Starts Regenerative
Action of the Positive-Feedback Loop of the Latch
What Happens When S=R=1 ???
Both NOR Gates will cause Q and Q to become 0
making Complementary labeling Incorrect.
However, if R and S return to Rest State (R=S=0)
precisely at the same time, the state of Flip-Flop will
be undefined. For this reason this input
Combination is Not Allowed.
In Practice one of the R and S returns to 0 first, and
the Final State is determined by the input that
Remains High Longest.
Truth Table:
Qn is Value of Q at Time tn just
before application of R and S
Signals.
Qn+1 is Value of Q at time tn+1 after
application of input Signals.
SR Flip-Flop can also be
implemented using two NAND
gates. In this case Set Reset
Functions are active when Low,
therefore labeled as S and R
11.1.3 CMOS Implementation of SR
Flip-Flop
• SR Flip-Flop can be directly implemented in
CMOS by just replacing each NOR gate by its
CMOS circuit realization
Clocked version of SR Flip-Flop using CMOS.
Except Clock Inputs, It operates exactly same
as the Logic Circuit scheme.
Clock inputs form AND Function with S and R,
therefore, Flip-flop can only be Set and Resent
when Clock is High.
To Set from Reset State: High (VDD) Signal on S while R
is Held at Low (0V). Now, When Clock Goes High both
Q5 and Q6 will conduct, Pulling Voltage at Q Down. When
V goes below threshold of (Q3,Q4) Inverter, It will begin
switching states and V at Q node will Rise. The
Increase at Q is Fed Back to the Input of (Q1, Q2)
Inverter, causing its Output at Q to go down further. The
regeneration process is in progress.
Flip-Flop switching (for Set) is predicted on following
two assumptions:
1. Q5 and Q6 supply sufficient current to pull node Q
at least slightly below threshold of (Q3 and Q4)
inverter. This is very important for the regenerative
process to begin. Example 11.1 investigates
minimum W/L ratios so that Q5 and Q6 must meet this
requirement.
2. The Set signal remains high for an interval long
enough to cause regeneration to take over the
switching process. An estimate of minimum width
required for the set pulse can be obtained as the
Sum of Interval during which voltage at Q is
reduced from VDD to VDD/2 and the interval for the
voltage at Q to respond and rise to VDD/2
Finally, due to symmetry all remarks apply equally
well to Reset process.
Example 11.1
11.1.4 Simpler CMOS Implementation of clocked SR Flip-Flop
• In simple implementation, Pass-Transistor Logic
is employed to implement the Clocked SR FlipFlop
• This ckt is very popular in the design of Static
Random-Access Memory (SRAM) chips, where it
is used as the Basic Memory Cell
In Next Class
We Will Discuss:
RAM and ROM Memories