Transcript lecture_digital_logic

Fundamentals of Digital Logic
B. Furman
25NOV2014
Mechatronics Concept Map
Power
Source
User
Interface
ME 106
ME 120
EE 118
Controller
(Hardware & Software)
ME 106
Power
Interface
INTEGRATION
ME 106
ME 154
ME 157
ME 195
Signal
Conditioning
ME 106
ME 190
ME 187
ME 106
ME 120
Actuator
Sensor
ME 120
ME 297A
System to
Control ME 110 ME 182
ME 136 ME 189
ME 154 ME 195
ME 157
BJ Furman 26JAN06
Digital Logic

Combinatorial Logic

The combination of logic states (0’s and 1’s) at the
inputs of logic gates (digital logic elements) determines
the output state according to the logic function.


AND, OR, NOT, XOR
NAND, NOR


Ex. 7447 BCD-to-7-segment decoder; ‘enable’ inputs
Sequential Logic

The combination of input logic states and their
sequencing determines the output state

Flip-flops

Ex. Computer memory, microcontroller registers
Review of Logic Functions

AND, OR, NOT, XOR, NAND, NOR
Truth Tables for Logic Functions
U1
Logic Function
OR
Logic Function
A
B
Z
A
B
Z
0
0
0
OR2
0
0
0
0
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
Logic Function
U1
NOR
Logic Function
Logic Function
A
Z
0
1
1
0
NOT
U
NAND
Logic Function
B
Z
A
B
Z
OR2
0
0
1
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
A
B
Z
0
0
1
0
1
1
1
A
AND
XOR
OR
Boolean Algebra Laws and Identities

See the handout
All logic functions can be formed
from NAND or NOR gates alone
Demorgan’s Theorem

You can swap shapes (AND or OR), if at the
same time you invert all inputs and outputs.
A B  A  B
Combinatorial Logic
The three logic functions, AND, OR, and
NOT can be used to build any digital
device
 NAND gates or NOR gates are universal,
i.e., can be used to construct the three
logic functions, hence any digital device


Ex.
Z
A
Internal Construction – Inverter (TTL)
A
Z
input
output
Logic Function
(Source: http://www.allaboutcircuits.com/vol_4/chpt_3/2.html)
A
Z
0
1
1
0
NOT
Inverter Operation
Input High (1)
Input Low (0)
5V
0V
(Source: http://www.allaboutcircuits.com/vol_4/chpt_3/2.html)
CMOS Inverter
http://www.allaboutcircuits.com/vol_4/chpt_3/7.html
Logic Chips - c. 1960’s and 1970’s

Multi-input versions exist

Examples:

7421 Dual 4-input AND

74LS00 Quad 2-input
NAND
http://www.oup.com/us/pdf/microcircuits/students/logic/74LS00-motorola.pdf
Logic Chips c. 1980 – pres.

Programmable logic devices (PLD)

Programmable Array Logic (PAL)
 Generic Array Logic (GAL)
Lattice Semiconductor c. 1985
 Erasable and reprogrammable
PAL device


Complex Programmable Logic
Device (CPLD)


More gates than PALs and GALS
Field Programmable Gate Array
(FPGA)
http://www.xess.com/appnotes/fpga_tut.php
Field Programmable Gate Array (FPGA)

A ‘programmable’ digital logic device

You define the logic functions in a Hardware
Descriptor Language (HDL)
 Compile the HDL description into a binary file
 Download the binary to the FPGA device
 Voila! You have a device that will execute
your logic function

For more information:

http://www.fpga4fun.com/index.html
Combinatorial Logic Circuit Design

Vote counting circuit
Digital Logic Families

See the handout
Sequential Logic

Output based on input values and their
sequencing



timing is important!
Will often use trigger signals, called ‘clock’ (Clk)
signals to trigger events
Flip-Flops (also known as bi-stables or latches)

Devices that can store and switch between binary states, 0 and 1
 Fundamental building block of all semiconductor memory and
processing in digital computers
 Made up of logic gates with feedback (some outputs are fed back to
inputs of other gates)
R-S Flip-Flop
S Q
S stand for ‘set’
R Q
 R stands for ‘reset’
 Q and Qbar are
complementary outputs

S
Q
R
Q
1
Inputs
S
Outputs
R
Q
Q
0
0
Q0(1)
1
0
1
0
0
1
0
1
1
1
S
0
tprop (inverter)
1
R
0
Q 0 (0)
tprop (NAND)
1
Q
0
tprop (NAND)
1
NA
Q
0
NA means ‘not allowed’
Time
tprop is the ‘propagation
delay time’, which is the
time it takes the logic gate
to change its output state
following a change in the
state of the input.
Triggering Flip-Flops


Often important to synchronize changes on a
clock signal
Types of clock signals to trigger on:



Level (no ‘wedge’ symbol. If no bubble, active HIGH.
With bubble, active LOW)
Negative edge (bubble+wedge): 1  0 transition
Positive edge (wedge): 0  1 transition
Inputs
Clk
Outputs
S
R

Q
Q
0
0

Q0
Q0
1
0

1
0
0
1

0
1
1
1
Active-LOW
Active-HIGH
(level
(level triggered)
triggered)
R-S
Flip-Flop
Flip-Flop
Negative
Edge-Triggered
R-SR-S
Flip-Flop
NA
NA means ‘not allowed’
 means activated on rising edge of clock signal (positive edge)
S
Q
Clk
R
Q
Other Types of Flip-Flops - 1
Truth Table

D Flip-Flop
(ex. 7474)
Preset
Clear
D
Clk
Q
Q
1
1
0

0
1
1
1
1

1
0
1
1
x
0
Q0
Q0
1
1
x
1
Q0
Q0
0
1
x
x
1
0
1
0
x
x
0
1
0
0
x
x
Ex. Positive edgetriggered D flip-flop
Preset
D
Q
Clk Q
Clear
What are ‘preset’ and ‘clear’?
NA
Single input is stored and presented to Q on
edge of clock pulse
Preset pulled low (“active low”) will set Q to 1
Clear pulled low (“active low”) will clear or reset
Q to 0
Scherz, Practical Electronics for Inventors, p. 688
Other Types of Flip-Flops - 2
Truth Table

JK Flip-Flop
(ex. 7476)
Preset
Clear
J
K
Clk
Q
Q
1
1
0
0

Q0
Q0
1
1
0
1

0
1
1
1
1
0

1
0
1
1
1
1

Toggle
1
1
x
x
0, 1
Q0
Q0
0
1
x
x
x
1
0
1
0
x
x
x
0
1
0
0
x
x
x
Positive edge-triggered
JK flip-flop
Preset
J
Q
Clk
K
Q
Clear
NA
Like RS flip-flop, where J is like S and K is like R, but can have both J and K high.
This will cause output to toggle (change state)
Scherz, Practical Electronics for Inventors, p. 692
Sequential Logic Applications - 1
Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2nd ed., McGraw-Hill, NY.
Sequential Logic Applications - 2
Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2nd ed., McGraw-Hill, NY.
Sequential Logic Applications - 3
Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics
and Measurement Systems, 2nd ed., McGraw-Hill, NY.
Preset
Clear
J
K
Clk
Q
Q
1
1
0
0

Q0
Q0
1
1
0
1

0
1
1
1
1
0

1
0
1
1
1
1

Toggle
1
1
x
x
0, 1
Q0
Q0
0
1
x
x
x
1
0
1
0
x
x
x
0
1
0
0
x
x
x
NA
Sequential Logic Applications - 4
A ‘T’ flip-flop is essentially a JK flip-flop
with J and K inputs tied HIGH and the
clock input tied to the T input
Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2nd ed., McGraw-Hill, NY.

See handout

Uses a flip-flop
 Many applications
Precision timing
 Pulse generation
 Sequential timing
 Time delay generation
 PWM

http://www.doctronics.co.uk/pdf_files/555an.pdf
555 Timer IC
http://www.555-timer-circuits.com/motor-pwm.html
7447 BCD to 7-segment Decoder