Transcript Document

The “we found out ‘waitless’ is a
service that Sprint mobile
offers, guess we can’t use that
name” Project: Presentation #4
Team M2:
Jared Dubin
Terry Garove
Alex Runas
Overall Project
Objective:
Table/bar service interface
controller chip
10/03/2007
Manager:
Panchalam Ramanujan
Structural Verilog
Project Status
Design proposal – complete
Architecture - complete
Name – honestly we haven’t worked on this at all in a while
Size estimates/basic floorplan - complete
RTL / Behavioral - complete
Structural – complete
Schematic – incomplete
Component layout – incomplete
Functional block layout – incomplete
Functional block LVS - incomplete
Updated FSM Flow
Design Decisions:
- Simple Full Adder-Array multiplier – not too fancy, easy (easier?) to
layout than a lot of alternatives, smaller (no need for speed
requirements)
- Necessary comparators able to be done in just a few simple gates
which was good
- FSM states consolidated as much as possible, kept to 4 bits to represent
13 total states to minimize both the number of flip-flops and amount of
output/next state logic – also that logic was reduced to the best of my
ability
- Not much more than this was decided recently – most of the
functionality/decisions had already been made by this point
A Structural Model
- Everything that is reasonable to be structural (i.e,. Not things like the
SRAM) represented structurally in verilog, and a test simulation which
adds 3 items, asks for assistance, removes one item, transmits the
remaining two, and wipes the SRAM at the end all works perfectly.
-Drove home a few points – notably the multiplier is really very large,
and the next-state/output logic for the FSM is very clunky right now but
on the other hand both are absolutely functional and honestly that
makes us all as a team very happy
- I have the structural files in my email if you really super duper want
to see every line of all of them, but that would be really boring for a
presentation, so I just included some sample segments on the next few
slides
A Structural Model (sample structures)
module multiplier (x, y, z);
input [17:0] x;
input [10:0] y;
output [28:0] z;
wire g;
assign g = 1'b0;
mult
m_0_0(x[0],y[0],g,g,z[0],c_out_0_0),
m_0_1(x[0],y[1],p_out_1_0,c_out_0_0,z[1],c_out_0_1),
m_0_2(x[0],y[2],p_out_1_1,c_out_0_1,z[2],c_out_0_2),
m_0_3(x[0],y[3],p_out_1_2,c_out_0_2,z[3],c_out_0_3),
m_0_4(x[0],y[4],p_out_1_3,c_out_0_3,z[4],c_out_0_4),
m_0_5(x[0],y[5],p_out_1_4,c_out_0_4,z[5],c_out_0_5),
m_0_6(x[0],y[6],p_out_1_5,c_out_0_5,z[6],c_out_0_6),
m_0_7(x[0],y[7],p_out_1_6,c_out_0_6,z[7],c_out_0_7),
m_0_8(x[0],y[8],p_out_1_7,c_out_0_7,z[8],c_out_0_8),
m_0_9(x[0],y[9],p_out_1_8,c_out_0_8,z[9],c_out_0_9),
m_0_10(x[0],y[10],p_out_1_9,c_out_0_9,z[10],c_out_0_10),
…………..
A Structural Model (sample structures)
….
// next state logic for bit A (most significant bit)
na4, na5);
….
and
a0(na0, order, view),
a1(na1, modify, done, not_getAssist),
a2(na2, viewcart, removeSignal),
a3(na3, readSRAM, not_doneRead),
a4(na4, wipeSRAM, not_doneRead),
a5(na5, waitforpaid, paid);
or
ao(NEXT_A, na0, na1, na2, transmit, sleep, remove, na3, searchSRAM,
SRAM (Jared has things to say about this, he is the SRAM guy)
Issues/Concerns: not TOO many…
- Mainly just one: our single-bit flip-flop seems to be an invention that
potentially doesn’t exist. Behavioral code follows:
module flipflop (in, out, clk, write_en, reset);
input in;
input
clk, write_en, reset;
output
reg out;
always @ (posedge clk)
begin
if (reset)
out <= 0;
else if(write_en)
out <= in;
else
out <= out;
end
endmodule // flipflop
So it is a positive-edge triggered DFF with a synchronous reset to 0
that only writes when write-enable is high. Seems reasonable?
Issues/Concerns: not TOO many…
- Apparently it isn’t. Our 3rd or 4th attempt at a structural FF:
module flipflop (in, out, clk, write_en, reset);
input in, clk, write_en, reset;
output out;
nand ga (a,in,i);
nand gb (b,a,i);
nand gc (c,a,d);
nand gd (d,c,b);
nand ge (e,c,j,k);
nand gf (f,e,j);
nand gg (out,e,qb);
nand gh (qb,out,f);
nand gi (i,clk,write_en);
not gj (j,i);
nand gk (k,clk,reset);
endmodule
On its own, it simulates just fine.
In the design as a whole, it has weird troubles resetting before it has
been written to, which makes it look like nothing is working right, and
we don’t want the input of every single register to have to be an input
so that we can reset them all on state-machine reset. Also, clock
gating? Not sure about that.
Issues/Concerns: not TOO many…
- We’ll almost definitely use a transistor-level flip-flop anyway: 9 or 10
NAND gates is absolutely huge size-wise if you can mimic the
functionality in ~14 transistors
-…but can we get this weird synchronicity to work with the FSM timing
that we’ve already designed, or is this flip flop doomed to flop?
- oh, and Jared couldn’t get Cadence to work right. He probably
already talked about that. Hopefully this can be amended.