Transcript ppt

User Guide of the
Input Trigger Multiplexer unit
with input signal rate counters.
F.F. - 18/07/2008
1
Rx Low card configuration
rxCH1
rxCH2
NOTE:
For Rx High card the only
change concerns the rxCH
number sequence:
rxCH3
rxCH14
rxCH4
rxCH15
rxCH5
rxCH16
rxCH6
rxCH7
rxCH17
rxCH18
rxCH19
rxCH1
becomes
rxCH26
rxCH2
becomes
rxCH27
……
…….
……
rxCH10
rxCH23
rxCH25
becomes
rxCH50
rxCH11
rxCH24
rxCH12
rxCH25
rxCH8
rxCH9
Termination
resistor
jumpers
rxCH20
rxCH21
rxCH22
rxCH13
External CLK
(daisy chain)
LSB
MSB
Base address range: 1F-00
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TxMux card configuration
txCH1
txCH2
txCH3
txCH14
txCH4
txCH15
txCH5
txCH16
txCH6
txCH7
txCH8
txCH9
txCH17
txCH18
txCH19
txCH20
txCH21
txCH22
txCH10
txCH23
txCH11
txCH24
txCH12
txCH25
txCH13
External CLK
(daisy chain)
LSB
MSB
Base address range: 1F-00
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3
Auxiliary P2 Backplane slots
FI card
FI card
GA=3 (2nd TxMux card)
GA=2 (Rx High card)
GA=1 (Rx Low card)
GA=0 (1st TXMux card)
(as seen from front of crate when plugged)
The auxiliary backplane is 4 slot wide and is plugged on the rear side of P2.
The 4 locations are identified by their Geographical Address pins (GA):
GA=0 is used by a 1st TxMux card
GA=1 and GA=2 are used for Rx cards
GA=3 is used by a 2nd TxMux card
The two rightmost locations are used by the trigger FanIn cards (no VME
addressing space)
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Logic diagram
Rx High card
rxCH50
50
50
1st TxMux card
Register
1 … 50
txCH25
IN rate counter
(r/o by VME)
txCH1
26
rxCH26
LHC CLK (external)
1
0 = OFF
GA = 2
LHC CLK (external)
Each Rx input channel has a rate counter that is
operated by a dedicated 32 bit register
Rx Low card
rxCH25
25
GA = 0
Each TxMux output channel has a 50 input multiplexer
that is operated by a dedicated 6 bit register
50
2nd TxMux card
Register
1 … 50
txCH25
IN rate counter
(r/o by VME)
txCH1
1
rxCH1
LHC CLK (external)
GA = 1
UD pins on auxiliary bus
(P2 connector and backplane)
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1
0 = OFF
LHC CLK (external)
GA = 3
5
VME space
Rx and TxMux cards are automatically selected by plugging them into the dedicated GA slots (note however
that Rx cards require manual insertion of terminator resistor jumpers – see page 2)
Rx Low and High cards do not require software configuration download for the Trigger Signal routing.
Rx cards need configuration to enable and select the IN Rate Counters. By default or reset all 25 counters
are switched OFF. Eight types of counting can be selected (see details at page 8).
An external clock source (LHC CLK) is necessary if counting has to be synchronized with the experiment
system clock. The input is at the front panel; it requires a NIM signal and a 50Ω termination at the end of the
daisy chained cable. The selection from internal free running clock and the external synchronous clock is
done automatically by the RX card (while an external clk signal is provided, the external clk is selected).
The phase of the external LHC CLK can be adjusted by VME in four steps of 90 degrees.
Tx Mux card 1 (i.e. plugged into GA=0) inverts the outputs, while Tx Mux card 2 (i.e. plugged into GA=3)
does not invert the outputs.
VME address space:
A24/D32
Base Addresses = from 1F00xxHex to 0000xxHex selectable by switches
Internal register addresses = from 00Hex to 64Hex (00, 04, 08, …, 60, 64)
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VME space
Description of Register 00 (control/status) for both Rx and TxMux cards:
Write:
bits 06, 05 = LHC_CLK Phase select (four steps of ¼ of period)
bit 0 = s/w reset -> puts the TxMux card in OFF state, i.e. all channels disabled
-> puts the Rx card in OFF state, i.e. all counters disabled
-> puts the external clock phase to 0 degrees
Read:
bit 07 = ON when PLL is unlocked
bits 06, 05 =
0,0 => phase 0 degrees
0,1 => phase 90 degrees
1,0 => phase 180 degrees
1,1 => phase 270 degrees
bit 04 = ON when LHC Clock is active (automatic selection by providing external clk)
bit 3 = ON when Rx High card
bit 2 = ON when Rx Low card
bit 1 = ON when TxMux card
bit 0 = ON for last s/w reset action, OFF after first read
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VME space
Description of Registers 04Hex (txCH1) to 64Hex (txCH25) (multiplexer selection) for TxMux cards only:
Write/Read:
bit 5 to bit 0 = selection of input channel (1 to 50)
(0, reset default = OFF; nn = select rx channel nn)
Description of Registers 04Hex (cntCH1) to 64Hex (cntCH25) for Rx cards only:
Write/Read:
bit 31 to bit 28 = selection of counting type
Counting types:
Read only:
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0 => counting OFF (reset default)
5 => counts pulses with width < 1 period
6 => counts pulses with width ≥ 1 period
7 => counts pulses with width = 1 period
A => counts pulses with width ≥ 2 periods
B => counts pulses with width = 2 periods
E => counts pulses with width ≥ 3 periods
F => counts pulses while level in ON
bit 25 to bit 0 = rate counter values (updated every second)
8
Front Panel
Reset = ON when operating manual reset button
VME Write = ON when TxMux card
VME Read = ON when Rx card (Low or High)
PLL Locked = ON when card selected by VME or reset by Power ON, SYSRST, Push button, S/W reset
External clock inputs LEMOs (NIM logic) are used if external synchronous clock is required.
This option is useful if users want synchronizing the rate counters to the LHC experiment system clock.
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