Transcript lec02-verilogintro

Digital System Design
Introduction to
Verilog® HDL
Maziar Goudarzi
Today program
• Hello World!
• Hierarchical Modeling Concepts
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Verilog® HDL
Hello World!
Basics of Digital Design Using HDLs
Stimulus block
Generating
inputs
to CUD
Circuit Under Design
(CUD)
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Checking
outputs
of CUD
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Test bench
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Typical Design
Flow for
Digital Systems
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ModelSim® Simulation Environment
• You’ll see later today
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Verilog Basic Building Block:
Module
module not_gate(in, out); // module name+ports
// comments: declaring port type
input in;
output out;
// Defining circuit functionality
assign out = ~in;
endmodule
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useless Verilog Example
module useless;
initial
$display(“Hello World!”);
endmodule
• Note the message-display statement
– Compare to printf() in C
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Verilog® HDL
Hierarchical Modeling Concepts
Design Methodologies
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4-bit Ripple Carry Counter
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T-flipflop and the Hierarchy
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Modules
module <module_name>(<module_terminal_list>);
...
<module internals>
...
endmodule
• Example:
module T_ff(q, clock, reset);
...
<functionality of T_flipflop>
...
endmodule
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Modules (cont’d)
• Verilog levels of abstraction
Behavioral
– Behavioral (algorithmic) level
• Describe the algorithm used
• (almost) C programming
Data flow
– Dataflow level
problem
• Flow of data among registers and
their processing
– Gate level
Structural
Switch
• Interconnect logic gates
– Switch level
• Interconnect transistors (MOS transistors)
• Register-Transfer Level (RTL)
– Behavioral + dataflow synthesizable by EDA
tools
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Module Instances (cont’d)
D Flip-Flop
// module DFF with asynchronous reset
module DFF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
always @(posedge reset or negedge clk)
if (reset)
q = 1'b0;
else
q = d;
endmodule
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Module Instances (cont’d)
T Flip-Flop
module TFF(q, clk, reset);
output q;
input clk, reset;
wire d;
DFF dff0(q, d, clk, reset);
not n1(d, q); // not is a Verilog provided primitive.
endmodule
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Module Instances
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4
TFF
TFF
TFF
TFF
instances of the module TFF are created.
tff0(q[0],clk, reset);
tff1(q[1],q[0], reset);
tff2(q[2],q[1], reset);
tff3(q[3],q[2], reset);
endmodule
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Module Instances (cont’d)
• Illegal instantiation example:
– Nested module definition not allowed
– Note: module definition vs. module instantiation
// Define the top level module called ripple carry counter.
// It is illegal to define the module T_FF inside this module.
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING
:
<module T_FF internals>
:
endmodule // END OF ILLEGAL MODULE NESTING
endmodule
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Simulation.
Test Bench Styles
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Example
• Design block
– ripple_carry_counter,
T_FF, and D_FF modules
• Stimulus block
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Example (cont’d)
module stimulus;
reg clk; reg reset; wire[3:0] q;
// instantiate the design block
ripple_carry_counter r1(q, clk, reset);
// Control the clk signal that drives the design block.
initial clk = 1'b0;
always #5 clk = ~clk;
// Control the reset signal that drives the design block
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
#20 $stop;
end
initial // Monitor the outputs
$monitor($time, " Output q = %d",
endmodule
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q);
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What we learned today
• An overview of Verilog programming (design)
concepts
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Other Notes
• Course web-page on Sharif Courseware
• Do it yourself (You won’t, I know! :-) )
– Read Chapters 1 and 2
– Do Chapter 2 exercises
– Install and use ModelSim, and simulate
ripple_carry_counter example
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Lexical Conventions
in Verilog® HDL
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Lexical Conventions
• Very similar to C
– Verilog is case-sensitive
– All keywords are in lowercase
– A Verilog program is a string of tokens
•
•
•
•
•
•
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Whitespace
Comments
Numbers
Strings
Identifiers
Keywords
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Lexical Conventions (cont’d)
• Whitespace
• Comments
– Blank space (\b)
– Tab (\t)
– Newline (\n)
– Used for readability and
documentation
– Just like C:
• Whitespace is ignored
in Verilog except
/*
/*
be
on
– In strings
– When separating tokens
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// single line comment
/* multi-line
comment
*/
Nested comments
like this */ may not
acceptable (depends
Verilog compiler) */
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Lexical Conventions (cont’d)
• Operators
– Unary operators precede the operand
a = ~b;
– Binary operators appear between two operands
a = b && c;
– Ternary operators have two separate operators that separate
three operands
a = b ? c : d; // the only ternary operator
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Lexical Conventions (cont’d)
• Number Specification
– Sized numbers
– Unsized numbers
– Unknown and high-impedance values
– Negative numbers
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Lexical Conventions (cont’d)
• Sized numbers
• Unsized numbers
– General syntax:
<size>’<base><number>
– Default base is decimal
– Default size is at least 32
(depends on Verilog compiler)
– Examples
• <size> :
number of bits (in decimal)
• <base> :
–
–
–
–
d or D for decimal (radix 10)
b or B for binary (radix 2)
o or O for octal (radix 8)
h or H for hexadecimal (radix 16)
• 23232
• ’habc
• ’o234
• <number> :
is the number in radix <base>
• Examples:
– 4’b1111
– 12’habc
– 16’d255
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Lexical Conventions (cont’d)
• X or Z values
– Unknown value: lowercase x
• 4 bits in hex, 3 bits in octal, 1 bit in binary
– High-impedance value: lowercase z
• 4 bits in hex, 3 bits in octal, 1 bit in binary
– Examples
• 12’h13x
• 6’hx
• 32’bz
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Lexical Conventions (cont’d)
• Negative numbers
– Put the sign before the <size>
– Two’s complement is used to store the value
– Examples:
• -6’d3
• 4’d-2
// illegal
• Underscore character and question marks
– Use ‘_’ to improve readability
• 12’b1111_0000_1010
• Not allowed as the first character
– ‘?’ is the same as ‘z’ (only regarding numbers)
• 4’b10?? // the same as 4’b10zz
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Lexical Conventions (cont’d)
• Strings
– As in C, use double-quotes
– Examples:
• “Hello world!”
• “a / b”
• “text\tcolumn1\bcolumn2\n”
• Identifiers and keywords
– identifiers (Identifiers are names given to objects so that they can be
referenced in the design)
• Alphanumeric characters, ‘_’, and ‘$’
• Should start with an alphabetic character or ‘_’
• Only system tasks can start with ‘$’
– Keywords
• Identifiers reserved by Verilog
– Examples:
reg value;
input clk;
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Lexical Conventions (cont’d)
• Escaped identifiers
–
–
–
–
–
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Start with ‘\’
End with whitespace (space, tab, newline)
Can have any printable character between start and end
The ‘\’ and whitespace are not part of the identifier
Examples:
• \a+b-c
// a+b-c is the identifier
• \**my_name** // **my_name** is the identifier
• \\n
// ???
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Data Types in Verilog® HDL
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Data Types
•
•
•
•
•
•
•
•
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Value set and strengths
Nets and Registers
Vectors
Integer, Real, and Time Register Data Types
Arrays
Memories
Parameters
Strings
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Value Set
• Hardware modeling requirements
– Value level
– Value strength
• Used to accurately model
–
–
–
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MOS devices
Dynamic MOS
Other low-level details
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There are two types of strengths: drive
strengths and charge strengths. The drive
strengths can be used for nets
(except trireg net) and gates. The charge
strengths can be used only for trireg nets.
The
drive
strength
types
are
supply,
strong,
pull,
weak,
and highz strengths. The charge strength
types
are large, medium and small strengths.
Drive strength is the capacity of a cell to
drive a value to the cell connected to its
output. Storage Strength is capacity to
store charge.
Value Set and Strength Levels
Value level HW Condition
Type
0
Logic zero, false
supply
Driving
1
Logic one, true
strong
Driving
pull
Driving
large
Storage
weak
Driving
medium
Storage
small
Storage
highz
High
Impedance
x
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Strength level
Unknown
High imp., floating
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If two signals of unequal strengths are
driven on a wire, the stronger signal
prevails. For example, if two signals of
strength strong1 and weak0 contend, the
result is resolved as a strong1. If two
signals of equal strengths are driven on a
wire, the result is unknown. If two signals
of strength strong1 and strong0 conflict,
the result is an x. Strength levels are
particularly useful for accurate modeling of
signal contention, MOS devices, dynamic
MOS, and other low-level devices. Only
trireg nets can have storage strengths
large, medium, and small
Net Data Type
• Used to represent connections between HW elements
– Values continuously driven on nets
• Keyword:
wire
– Default: One-bit values
• unless declared as vectors
– Examples
• wire a;
• wire b, c;
• wire d=1’b0;
– Default value: z
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• Net data types are used to model physical
connections. They do not store values (there is
only one exception - trireg, which stores a
previously assigned value). The net data types
have the value of their drivers. If a net variable
has no driver, then it has a high-impedance
value (z).
•
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Register Data Types
• Registers represent data storage elements
– Retain value until next assignment
– NOTE: this is not a hardware register or flipflop, In Verilog,
the term register merely means a variable that can hold a
value
– Keyword:
reg
– Default value: x
– Example:
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reg reset;
initial
// this will be explained later
begin
reset = 1’b1; //initialize reset to 1 to reset the digital
#100 reset=1’b0;
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end
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Types of Registers
• Integer
– Keyword:
integer
• integer variables are signed numbers
• reg vectors are unsigned numbers, unless specified
– reg signed [63:0] m; // 64 bit signed value
– Bit width: implementation-dependent (at least 32-bits)
• Designer can also specify a width:
integer [7:0] tmp;
– Examples:
integer counter;
initial
counter = -1; //A negative one is stored in the counter
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Register Types (cont’d)
• Real
– Keyword: real
– Values:
• Default value: 0
• Decimal notation: 12.24
• Scientific notation: 3e6 (=3x106)
– When a real value is assigned to an integer, the real number is rounded off to the
nearest integer.
– Example:
real delta;
initial
begin
delta = 4e10;
delta = 2.13;
end
integer i;
initial
#5 i = delta; // i gets the value 2 (rounded value of 2.13)
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Register Data Types (cont’d)
• Time
–
–
–
–
–
Used to store values of simulation time
Keyword:
time
Bit width: implementation-dependent (at least 64)
$time system function gives current simulation time
Example:
time save_sim_time; // Define a time variable
initial
save_sim_time = $time; // Save the current simulation time
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Vectors
• Nets or reg data types can be declared as vectors (multiple bit widths). If
bit width is not specified, the default is scalar (1-bit).Applicable to both
net and register data types
• Syntax:
– wire/reg [msb_index : lsb_index] data_id;
• Examples
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:0] busA,busB,busC; // 3 buses of 32-bi
reg clock; // scalar register, default
reg [0:40] virtual_addr; //virtual address 41bits
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Vectors (cont’d)
• Bit-select and part-select allowed:
busA[7] // selects bit #7 of vectorbus A
busB[2:0] //three least-significant bits-ofbusB
bus[0:2] // illegal
virtual_addr[0:1] /* two most-significant bits
* of virtual_addr
*/
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Vectors( cont’d)
Variable Vector Part Select
reg [255:0] data1; //Little endian notation
reg [0:255] data2; //Big endian notation
reg [7:0] byte;
//Using a variable part select,
byte = data1[31-:8]; //starting
byte = data1[24+:8]; //starting
byte = data2[31-:8]; //starting
byte = data2[24+:8]; //starting
one
bit
bit
bit
bit
can choose parts
= 31, width =8 =>
= 24, width =8 =>
= 31, width =8 =>
= 24, width =8 =>
data1[31:24]
data1[31:24]
data2[24:31]
data2[24:31]
//The starting bit can also be a variable. The width has
//to be constant. Therefore, one can use the variable part select
//in a loop to select all bytes of the vector.
for (j=0; j<=31; j=j+1)
byte = data1[(j*8)+:8]; //Sequence is [7:0], [15:8]... [255:248]
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Arrays
• Allowed for all data types
• Multi-dimensional
• Syntax:
<data_type> <var_name> [start_idx : end_idx]
[start_idx : end_idx] ...
[start_idx : end_idx];
• Examples:
integer
reg
reg [4:0]
integer
count[0:7]; // An array of 8 count variables
bool[31:0]; // Array of 32 one-bit boolean register
port_id[0:7];//Array of 8 port_ids;each port_id is 5 bits wide
matrix[4:0][0:16]; // Two dimensional array of integers
• Difference between vectors and arrays
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Arrays (cont’d)
• Examples (cont’d)
count[5] = 0; // Reset 5th element of array of count variables
chk_point[100] = 0; // Reset 100th time check point value
port_id[3] = 0; // Reset 3rd element (a 5-bit value) of port_id array.
matrix[1][0] = 33559; // Set value of element indexed by [1][0] to 33559
port_id
= 0; // Illegal
matrix [1] = 0; // Illegal
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Memories
• RAM, ROM, and register-files used many times in digital
systems
• Memory = array of registers (register data type) in Verilog
• Word = an element of the array
– Can be one or more bits
• Examples:
reg membit [0:1023]; // Memory mem1bit with 1K 1-bitwords
reg [7:0] membyte[0:1023];
//Memory membyte with 1K 8-bit words(bytes)
membyte[511] //Fetches 1 byte word whose address is511
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Strings
• Strings are stored in reg vectors.
• 8-bits (1 byte) required per character
• Stored from the least-significant part to the most-significant part
of the reg vector
• Example:
reg [8*18:1] string_value;
// Declare a variable that is 18 bytes wide initial
initial
string_value = “Hello World!”;
• Verilog allows constants to be defined in a module by the
keyword parameter.
• parameter port_id = 5; // Defines a constant port_id
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Have you learned this topic?
• Various data types
– 4-valued logic: 0, 1, x, z
– Strength levels
– Register vs. Net data types
• reg, integer, real, time register data types
• wire data type
– Vectors
– Arrays
– Strings
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