Transcript 2102-282 Digital Electronics - IC Design & Application Research Lab.

Chapter 7
Sequential Circuits
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
August 20, 2004; Revised - July 4, 2005
B.Supmonchai
Goals of This Chapter

Implementation techniques for
 Register: latches and flipflops
 Schmitt Triggers
 Oscillator, pulse generators

Static versus Dynamic Realization

Clocking Strategies
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Sequential Logic
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Q
State
Register
D
CLOCK
Storage Mechanisms
Positive Feedback
STATIC
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Charge-Based
DYNAMIC
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Static vs Dynamic Storage

Static storage
 preserve state as long as the power is on
 have positive feedback (regeneration) with an internal
connection between the output and the input
 useful when updates are infrequent (clock gating)

Dynamic storage
 store state on parasitic capacitors
 only hold state for short periods of time (milliseconds)
 require periodic refresh
 usually simpler, so higher speed and lower power
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Latches versus Flipflops

Latches (with Clock)
 level sensitive circuit that passes inputs to Q when the clock is
high (or low) - transparent mode
 input sampled on the falling edge of the clock is held stable
when clock is low (or high) - hold mode

Flipflops (edge-triggered)
 edge sensitive circuits that sample the inputs on a clock
transition
 positive edge-triggered: 0  1
 negative edge-triggered: 1  0
 built using latches (e.g., master-slave flipflops)
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Review: The Regenerative Property
Vi1
Vo1
Vi2
Vo2

Small deviation from
bias point C (e.g., from
noise) is amplified and
regenerated around the
circuit loop until either
point A or B is reached

If the gain in the
transient region is larger
than 1, only A and B are
stable operation points.
C is a metastable
operation point.
Cascaded Inverters
A
C
B
Vi1 = Vo2
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Review: Bistable Circuits


The cross-coupling of two
inverters results in a
bistable circuit (a circuit
with two stable states)
Vi1
Vi2
Have to be able to change the stored value by making A
(or B) temporarily unstable by increasing the loop gain
to a value larger than 1
 done by applying a trigger pulse at Vi1 or Vi2
 the width of the trigger pulse need be only a little larger than
the total propagation delay around the loop circuit (twice the
delay of an inverter)
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Review: SR Latch
S
R
2102-545 Digital ICs
!Q
Q
S
R
Q
!Q
Action
0
0
Q
!Q
memory
1
0
1
0
set
0
1
0
1
reset
1
1
0
0
disallowed
Sequential Logic
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Review: Clocked D Latch
D
!Q
D
Q
Q
clock
clock
transparent mode
In our course
All latches mean
clocked latches
clock
hold mode
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Latches versus Flipflops II

Latch

stores data when
clock is low (high)
stores data when
clock rises (falls)
D Q
D Q
Clk
Clk
Clk
Clk
D
D
Q
Q
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Flipflop
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Positive and Negative Latches
Positive Latch
In
D
Q
Negative Latch
In
Out
G
G
Clk
Clk
Clk
Clk
In
In
Out
Out
Out
Stable
2102-545 Digital ICs
D
Out
Follow In
Out
Stable
Out
Follow In
Sequential Logic
Out
Stable
Out
Follow In
Q
Out
Out
Stable
Out
Follow In
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Latch-Based Design
• N latch is transparent
when f = 0
• P latch is transparent
when f = 1
f
N
Latch
Logic
P
Latch
Logic
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Timing Metrics
clock
clock
tsu
In
time
thold
data
stable
time
tc-q
Out
output
stable
output
stable
time
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Timing Definitions

Setup time, tsetup is the time that the data inputs
(D) must be valid before the clock transition
 0 to 1 transition for a positive edge-triggered device
 1 to 0 transition for a negative edge-triggered device

Hold time, thold is the time that the data inputs
must remain valid after the clock edge

Propagation Delay, tc-q is the worst case
propagation delay (with reference to the clock
edge)
 time to copy D to Q
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System Timing Constraints
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Next state
Q
State
Register
D
T (clock period)
CLOCK
tcd: contamination delay = minimum delay
tcdreg + tcdlogic  thold
2102-545 Digital ICs
T  tc-q + tplogic + tsu
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Notes on System Timing Constraints

It is important to minimize the values of the timing
parameters associated with the register.

In modern high-performance systems, the register
propagation delay and set-up times account for a
significant portion of the clock period.
 DEC Alpha EV6 has a maximum logic depth of 12 gates and
the register overhead accounts for about 15% of the clock
period.

Hold time becomes an issue when there is little logic
between registers or when the clocks at different
registers are somewhat out of phase due to clock skew.
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Building A (Static) Latch
For a latch, use the clock as a decoupling signal, that
distinguishes between the transparent and opaque states
CLK
CLK
Q
D
CLK
D
CLK
D
CLK
Cutting the feedback loop
(Mux-based latch)
2102-545 Digital ICs
can implement as NMOS-only
Overpowering the feedback loop
(as in Static RAM)
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MUX Based Latches

Change the stored value by cutting the feedback loop
feedback
feedback
1
0
Q
D
Q
0
D
clk
1
clk
Positive Latch
Negative Latch
Q = clk & Q | !clk & D
Q = !clk & Q | clk & D
transparent when the
clock is low
transparent when the
clock is high
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TG MUX Based Latch Implementation
clk
Positive Latch
Q
input sampled
(transparent mode)
!clk
D
clk
clk
clk load is two transistors (and two
for !clk) = clock load of 4
!clk
Having to generate both clk and !clk
(nonoverlapping clocks)
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Sequential Logic
feedback
(hold mode)
19
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PT MUX Based Latch Implementation
clk
!Q
Q
D
input sampled
(transparent mode)
!clk
clk
Reduced clock load, but
threshold drop at output of
pass transistors so reduced
noise margins and performance
2102-545 Digital ICs
!clk
Sequential Logic
feedback
(hold mode)
20
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Latch Race Problem
B
B’
B
clk
clk
Which value of B is stored?
T  tc-q + tplogic + tsu
Thigh  tc-q + tcdlogic
2102-545 Digital ICs
Two-sided clock constraint
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Master Slave Based ET Flipflop
D
Q
0
1
D
Q
QM
0
clk
1
clk
clk
clk
Slave
D
Master
clk = 0
transparent
hold
clk = 1
hold
transparent
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Sequential Logic
QM
Q
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MS ET Implementation
Slave
Master
I2
I3
T2
I5
T4
I4
T3
I6
Q
QM
D
I1
T1
20 Transistors*
8 clock loads
clk
* Ignore clk buffer
master transparent
slave hold
clk
master hold
slave transparent
!clk
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MS ET Timing Properties

Assume propagation delays are tpd_inv and tpd_tx, that the
contamination delay is 0, and that the inverter delay to
derive !clk is 0

Set-up time - time before rising edge of clk that D must
be valid
tsu = 3 * tpd_inv + tpd_tx

Propagation delay - time for QM to reach Q
tpd = tpd_inv + tpd_tx

Hold time - time D must be stable after rising edge of clk
thold = 0
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Notes on MS ET Timing Properties

Set-up time
 How long before the rising edge does D have to be stable such
that QM samples the value reliably?
 D has to propagate through I1, T1, I3 and I2 before the rising
edge to ensure that the node voltages on both terminals of T2
are the same value.

Propagation delay time
 Since the delay of I2 is included in the set-up time, the output
of I4 is valid before the rising edge of clk, so the delay is
simply the delay through T3 and I6

Hold time
 since T1 turns off when the clock goes high, any changes in D
after clk goes high are not seen, so hold time is 0
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Set-up Time Simulation
3
Q
2.5
QM
Volts
2
1.5
1
D
tsetup = 0.21 ns
clk
0.5
I2 out
0
-0.5
0
0.2
0.4
0.6
0.8
1
Time (ns)
works correctly
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Set-up Time Simulation II
3
Q
2.5
I2 out
Volts
2
1.5
1
D
tsetup = 0.20 ns
clk
0.5
QM
0
-0.5
0
0.2
0.4
0.6
0.8
1
Time (ns)
Fails!
2102-545 Digital ICs
the clock is enabled before the nodes on both sides
of the transmission gate T2 settle to the same value
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Propagation Delay Simulation
tc-q (LH) = 160 psec
3
tc-q (HL) = 180 psec
2.5
Volts
2
Clk
1.5
1
D
tc-q (LH)
Q
tc-q (HL)
0.5
0
-0.5
0
0.5
1
1.5
2
2.5
Time (ns)
propagation delay is measured from the 50% point
of the clk edge to the 50% point of the Q output
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Reduced Load MS ET FF

Clock load per register is important since it directly
impacts the power dissipation of the clock network.

Can reduce the clock load (at the cost of robustness) by
making the circuit ratioed
I3
I1
D
QM
T
1
T
2
I2
!clk
12 Transistors
4 clock loads
!clk
clk
clk
Q
I4
reverse conduction
 to switch the state of the master, T1 must be sized to overpower I2
 to avoid reverse conduction, I4 must be weaker than I1
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Non-Ideal Clocks

Clk and !clk are never perfect inversions of one another
 We must generate !clk and route both signals
 Variations can exist in the wires used to route the two clock
signals and load capacitances may vary

Non-ideal clocks create skew resulting in clock overlap
1-1 Overlap
clk
clk
!clk
!clk
Ideal clocks
2102-545 Digital ICs
0-0 Overlap
Non-Ideal clocks
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Example of Clock Skew Problems
X
clk
Q
!clk
Race
D
P1
A
I2
I1
P3
B
I3
I4
P2
P4
!clk
clk
!Q
Race condition – direct path from D to Q during the short time
when both clk and !clk are high (1-1 overlap)
Undefined state – both B and D are driving A when clk and !clk
are both high
Dynamic storage – when clk and !clk are both low (0-0 overlap)
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Pseudostatic Two-Phase ET FF
X
clk1
D
P1
A
I2
I1
P3
B
P2
clk2
master transparent
slave hold
clk1
Q
clk2
dynamic
storage
tnon_overlap
I3
I4
!Q
P4
clk1
master hold
slave transparent
clk2
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Two Phase Clock Generator
A
clk1
clk
B
clk2
clk
A
B
clk1
clk2
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Power PC Flipflop
!clk
clk
1D
01
!clk
10
10
clk
master transparent
slave hold
clk
16 Transistors
8 clock loads
master hold
slave transparent
!clk
2102-545 Digital ICs
Q 01
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Overpowering The Feedback Loop
Clocked SR Latch
Cross-coupled NANDs
S
M2
M4
Q
Q
!Q
R
Q
clk
M6
M1
S
M8
clk
M7
R
M3
M5
This is not used in datapaths any more,
but is a basic building block for memory cell
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Ratioed CMOS Clocked SR Latch
off  on
on  off
M2
M4
Q 1 0
1  0 !Q
off ->on
0  1 clk
off ->on
M6
M1
0 S
on  off
clk 0  1
M7
R 1
M3
off  on
M5
on
off

M8
8 Transistors
2 Clock loads*
* sized
No static power consumption, but a ratioed device
where sizing is critical to ensure proper functionality
 M7, M8 must overcome M4 to bring Q low, so must M5, M6
over M2
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Sizing Issues
(W/L)2 and 4 = 1.5m/0.25 m
(W/L)1 and 3 = 0.5m/0.25 m
2
!Q (Volts)
1.5
so (W/L)5 and 6 > 3
1
0.5
0
2
2.5
3
3.5
4
(W/L)5 and 6
Output voltage depends on pull-down transistor width
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Transient Response
!Q (Volts)
3
!Q
S
W=0.5 µm
W=0.6 µm
W=0.7 µm
2
1
W=0.8 µm
W=1 µm
W=0.9 µm
0
0
0.4
0.8
1.2
1.6
2
Time (ns)
Individual device ratio for M5 or M6 must be larger than approx. 6.
Analysis results give 2.26 (instead of 3) since it doesn’t take into account
channel length modulation and DIBL (drain induced barrier loading).
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6 Transistor CMOS SR Latch
clk
clk
Problems with noise
margins and static
power consumption
due to threshold drop
across pass transistors

Once again, sizing is
important - especially
M5 and M6
S
R
clk
clk
M2
M4
Q
R

M5
!Q
M1
2102-545 Digital ICs
M6
S
M3
6 Transistors
2 Clock loads
Sequential Logic
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Review: Storage Mechanisms
Dynamic
(charge-based)
Static
(Positive Feedback)
CLK
CLK
Q
D
Q
CLK
D
CLK
CLK
Useful when update is infrequent
2102-545 Digital ICs
Simpler, Faster, and Lower Power
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Dynamic ET Flipflop
master
slave
!clk
D
clk
T1
I1
QM
T2
C
1
clk
I2
Q
C
!clk
2
tsu = tpd_tx
thold = zero
tc-q = 2 tpd_inv + tpd_tx
master transparent
slave hold
clk
!clk
2102-545 Digital ICs
8 Transistors
4 Clock loads
master hold
slave transparent
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Dynamic ET FF Race Conditions
!clk
clk
QM
D
T1
I1
T2
C
clk
clk
!clk
1
I2
Q
C
!clk
2
0-0 overlap race condition
toverlap0-0 < tT1 + tI1 + tT2
1-1 overlap race condition
toverlap1-1 < thold
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Dynamic Two-Phase ET FF
clk1
clk2
QM
T1
D
T2
I1
C
!clk1
I2
Q
C
1
!clk2
2
master transparent
slave hold
clk1
tnon_overlap
clk2
master hold
slave transparent
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Pseudostatic Dynamic Latch

Robustness considerations limit the use of dynamic FF’s
 Coupling between signal nets and internal storage nodes can
inject significant noise and destroy the FF state
 Leakage currents cause state to leak away with time
 Internal dynamic nodes don’t track fluctuations in VDD that
reduces noise margins

A simple fix is to make the circuit pseudostatic
clk
D
Slight increase in delay
(adds to the capacitive
load) and power
consumption, but it
improves noise immunity
significantly
T1
!clk
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C2MOS (Clocked CMOS) ET Flipflop
Master
Slave
M2
on
clk
M4
off
D
on
M3
!clk
QM
C1
off
!clk
M8
on
off
clk
M7
Q
C2
on
off
M1
M5
master transparent
slave hold
clk
!clk
2102-545 Digital ICs
8 Transistors
4 Clock loads
M6
Insensitive to clock
overlap as long as the
rise and fall times of
the clock edges are
sufficiently small
master hold
slave transparent
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C2MOS FF 0-0 Overlap Case
M2
0
M4
D
M3
M6
QM
0
Q
C1
M7
M1
C2
M5
clk
clk
!clk
!clk
2102-545 Digital ICs
M8
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Notes on C2MOS FF 0-0 Overlap Case

Does any new data sampled during the overlap window
propagate to Q (race)?
 New data is sampled on QM, but cannot propagate to Q since
M7 is off (slave is in hold).
 Any new data sampled on the falling clock edge is not seen at Q

For clocking on the left: at the end of the overlap period
!clk = 1 and both M7 and M8 turn off, putting the slave
in the hold mode

For the clocking on the right: at the end of the overlap
period clk = 1 and both M3 and M4 turn off, putting the
master in the hold mode (affects setup time as well)

The result: the FF is slower (slower tc-q time)
2102-545 Digital ICs
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C2MOS FF 1-1 Overlap Case
M2
M4
D
1
M3
M6
M8
QM
C1
Q
1
M1
M7
C2
M5
clk
clk
!clk
!clk
1-1 overlap constraint: toverlap1-1 < thold
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Notes on C2MOS FF 1-1 Overlap Case

New data is sampled on QM, but cannot propagate to Q
since M8 is off (slave is in hold).

A bit more problematic than 0-0 overlap.
 It must enforce a hold time on D, so that changing D which
reaches QM is not copied to Q when overlap time is over
-
 first clocking condition.
 By imposing a hold time on D - that D must be stable during
clock overlap - overcome this problem as well

However, possible race can occur if the rise/fall times of
the clock are sufficiently slow.
 Works correctly as long as the clock rise/fall times is smaller
than approximately five times the propagation delay of the
flipflop.
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C2MOS Transient Response
3
QM(3)
2.5
Q(3)
2
1.5
Q(0.1)
1
clk(0.1 ns)
0.5
clk(3 ns)
0
-0.5
0
2
4
6
8
Time (nsec)
For slow clocks, potential for a race condition exists
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True Single Phase Clocked (TSPC) Latches
Negative Latch
Positive Latch
Q
clk
In
clk
Q
In
hold when clk = 1
transparent when clk = 0

clk
clk
transparent when clk = 1
hold when clk = 0
Uses only a single clock
 No clock overlap (skew) to worry about ; reduced clock load
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Embedding Logic in TSPC Latch
A
PUN
B
Q
In
clk
clk
Q
clk
clk
A
PDN
B
A AND B

Logic can be embedded into latch (or FF)
 Reduce delay overhead associated with the latch
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Notes on Embedding Logic in TSPC Latch

Set-up time increased, but overall performance
improved
 The increase in the set-up time is typically smaller than the
delay of an AND gate.
 For example, using minimum size devices set-up of AND latch
is 140 psec.
 Using the conventional approach of AND gate followed by
latch has an effective set-up time of 600 psec.

Technique used extensively in the design of the EV4
DEC Alpha microprocessor and many other high
performance processors.
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TSPC ET FF
Master
D
clk
on
off
clk
Slave
on
QM
off
on
clk off
on
clk
Q
off
12 Transistors
4 Clock loads
master transparent
slave hold
master hold
slave transparent
clk
Virtually all constraints removed - no clocks to overlap, no race
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Notes on TSPC ET FF

Warning! - similar to C2MOS, TSPC flipflops
malfunction when the slope of the clock is not
sufficiently steep.
 Slow clock cause both the NMOS and PMOS
clocked transistors to be ON simultaneously,
resulting in undefined values of the states and race
conditions.
 Clock slopes thus must be carefully engineered. If
necessary, local buffers must be introduced to ensure
the quality of the clock signal
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Simplified TSPC ET FF
I1
clk
I3
off
on
M6
M9
Y1D
clk
on X !D
clk
off M2
off
M5
on M8
clk
M1
Moff
M7
4
on
M3
D
I2
9 Transistors*
4 Clock loads
I1 sample (transparent)
I2 precharged
I3 hold
*(11 if Q is needed)
I1 hold
I2 evaluate
I3 sample (transparent)
clk
2102-545 Digital ICs
Q D
Sequential Logic
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Notes on TSPC ET FF

On the positive edge of the clock, note that the node X
transitions to a low if D is high. Therefore, the input
must be kept stable until the value on node X before the
rising edge of the clock propagates to Y
 Hold time of the register (less than 1 inverter delay since it
takes 1 inverter delay for the input to affect node X).


Propagation delay is essentially three inverters since
the value on node X must propagate to output Q
Set-up time is the time for node X to be valid – one
inverter delay
2102-545 Digital ICs
Sequential Logic
57
B.Supmonchai
Sizing Issues in Simplified TSPC ET FF
clk
3
!Qmod
Transistor sizing
!Qorig
2
Original width
M4, M5 = 0.5m
M7, M8 = 2m
1
Qmod Qorig
0
0
0.2
0.4
0.6
0.8
Time (nsec)
1
Modified width
M4, M5 = 1m
M7, M8 = 1m
Sizing is critical – with improper sizing glitches may occur due
to race condition when the clock transitions from low to high
2102-545 Digital ICs
Sequential Logic
58
B.Supmonchai
Split-Output TSPC Latches
Positive Latch
Negative Latch
Q
In
clk
A
In
A
clk
Q
transparent when clk = 1
hold when clk = 0
hold when clk = 1
transparent when clk = 0
When In = 0, A = VDD - VTn
When In = 1, A = | VTp |
2102-545 Digital ICs
Sequential Logic
59
B.Supmonchai
Split-Output TSPC ET FF
8 Transistors*
2 Clock loads
*(10 if Q is needed)
D
clk
A
clk
QM
Q
Which edge-triggered?

Downside is not all node voltages in the latch experience
full logic swing due to threshold drop.
 E.g., for positive latch when D=0 and clk=1, A=Vdd-Vth (Also
limits the amount of Vdd scaling possible with this latch).
2102-545 Digital ICs
Sequential Logic
60
B.Supmonchai
Pulse-Triggered Flipflops

Another approach to design an edge-triggered
flipflop is to use pulse-triggered.
Master-Slave Flipflop
L1
Data
D
Clk
Q
Pulse-Triggered Flipflop
L2
D
L
Q
Clk
Data
Clk
D Q
Clk
Clk
2102-545 Digital ICs
Sequential Logic
61
B.Supmonchai
Pulsed FF (AMD-K6)

Pulse registers - a short pulse (glitch clock) is generated
locally from the rising (or falling) edge of the system
clock and is used as the clock input to the flipflop
OFF
clk
1
0
0/Vdd
P1ON X Vdd
P3
M3OFF
M6OFF
ON
1/0
D
1
1
1/0
P2
M5
OFF
1
0
2102-545 Digital ICs
Q
ON
M2ON/
0
ON/OFF
M1ON
!clkd
M4
ON
OFF
Sequential Logic
62
B.Supmonchai
Notes on Pulsed FF

Race conditions are avoided by keeping the transparent
mode time very short (during the pulse only)

Reduce clock load but substantially increase complexity
in verification

The transparency period determines the hold time.
 The window must be wide enough for the input data to
propagate to Q.

The set-up time can be NEGATIVE (if the transparency
window is longer than the delay from input to output).
 This is attractive, as data can arrive at the register even after
the clock goes high, meaning that time can be borrowed from
the previous cycle.
2102-545 Digital ICs
Sequential Logic
63
B.Supmonchai
Sense Amp FF (StrongArm SA100)

Sense amplifier is a circuit that accept small swing input
signals and amplify them to full rail-to-rail signals
0 1
1
D
X
M2
1
M5
0
M9
M7
!S
Q
M1
M4
!R
1
M3
0
Y
M6
1
M8
M10
0 1
clk
2102-545 Digital ICs
1
!Q
Sequential Logic
64
B.Supmonchai
Notes on Sensed Amp FF

The key is transistor M4 (in the middle of Sensed amp);
it delays signals that pass through to the other side of its
terminal, making the change on the other side slower
 When D = 1, Y changes after X due to the delay of M4. By the
time M6 reacts to the change at its terminal, it is already
turned off by the terminal voltage at M4 (a 0). Thus, M6 holds
a 1.

M4 also provides DC-leakage path to ground for either
node X or Y in case that the inputs change their value
after the positive edge of CLK arrives.

Advantages are reduced clock load and that it can be
used as a receiver for reduced swing differential buses
 Where does the differential signal enter?
2102-545 Digital ICs
Sequential Logic
65
B.Supmonchai
Flipflop Comparison Chart
Name
Type
#clk ld
#tr
tset-up
thold
tpFF
Mux
Static
8 (clk-!clk)
20
3tpinv+tptx
0
tpinv+tptx
PowerPC
Static
8 (clk-!clk)
16
2-phase
Ps-Static
8 (clk1-clk2)
16
T-gate
Dynamic
4 (clk-!clk)
8
C2MOS
Dynamic
4 (clk-!clk)
8
TSPC
Dynamic
4 (clk)
11
S-O TSPC
Dynamic
2 (clk)
10
AMD K6
Dynamic
5 (clk)
19
SA 100
SenseAmp
3 (clk)
20
2102-545 Digital ICs
Sequential Logic
tptx
to1-1 2tpinv+tptx
tpinv
tpinv
3tpinv
66
B.Supmonchai
Choosing a Clocking Strategy

Choosing the right clocking scheme affects the
functionality, speed, and power of a circuit

Two-phase designs
 + robust and conceptually simple
 - need to generate and route two clock signals
 - have to design to accommodate possible skew between the
two clock signals

Single phase designs
 + only need to generate and route one clock signal
 + supported by most automated design methodologies
 + don’t have to worry about skew between the two clocks
 - have to have guaranteed slopes on the clock edges
2102-545 Digital ICs
Sequential Logic
67
B.Supmonchai
Non-Bistable Sequential Circuits

Previously, we have defined a circuit having two
stable states a bi-stable circuit

Other regenerative circuits, which are nonbistable:
 Monostable
 Only one stable state -> Pulse generators, One-shot circuits
 Astable
 No stable states -> Oscillator, On-chip clock generator
 Schmitt Trigger
 A special regenerative circuit exhibiting hysteresis in VTC.
2102-545 Digital ICs
Sequential Logic
68
B.Supmonchai
Schmitt Trigger
Non-Bistable Sequential Circuits
V OH
Vou t
In
Out
2 important properties
V OL
 Hysteresis
 Fast Transition Time
at the output
2102-545 Digital ICs
VM–
Sequential Logic
VM+
Vi n
69
B.Supmonchai
Noise Suppression using Schmitt Trigger
VIN
VOUT
VM+
VM-
t0
t
t0 + tp
t
Example: Switch Debouncer
2102-545 Digital ICs
Sequential Logic
70
B.Supmonchai
CMOS Schmitt Trigger
VDD
M2
Moves switching
threshold of the
first inverter
M4
X
VIN
M1
VOUT
M3
Low-to-High
reff = kM1/(kM2 + kM4)
High-to-Low
reff = (kM1 + kM3)/kM2
Adapting the ratio between PMOS and NMOS, depending upon the
direction of the transition results in a shift in switching threshold
2102-545 Digital ICs
Sequential Logic
71
B.Supmonchai
Schmitt Trigger Simulated VTC
M1 = 1 m/0.25 m, M2 = 3 m/0.25 m, M3 = 0.5 m/0.25 m
M4 = k x 0.5 m/0.25 m
2.5
2.5
2.0
2.0
VM1
1.5
1.0
Vout(V)
Vout(V)
M4 = 1.5 m/0.25 m
VM2
1.5
1.0
k=1
k=3
0.5
0.0
0.0
k=2
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
Voltage Transfer Characteristics
with hysteresis
2102-545 Digital ICs
0.0
0.0
k=4
0.5
1.0
1.5
Vin (V)
2.0
2.5
Effect of varying the ratio of the
PMOS device M4
Sequential Logic
72
B.Supmonchai
CMOS Schmitt Trigger (2)
How does the gate operate?
M4
M6
M3
VOUT
VIN
M2
M5
X
M1
Sketch VTC and find expression for VM- and VM+
2102-545 Digital ICs
Sequential Logic
73
B.Supmonchai
Review: Ring Oscillator
tp
Period: T = 2 x tp x N
Different Clock Duty-Cycles
and phases can be derived
using simple logic operations
2102-545 Digital ICs
Sequential Logic
74
B.Supmonchai
Voltage Controller Oscillator (VCO)

Oscillation frequency of a VCO is a function (typically
nonlinear) of a control voltage
VD D
VDD
M6
M4
Schmitt Trigger
restores signal slopes
M2
In
M1
Iref
Vcontr
Iref
M3
M5
Current starved inverter
(nsec)
Delay of6a current starved inverter depends on the current
limit available to discharge the load capacitance of the gate
L
2102-545 Digital ICs
4
Sequential Logic
75
Vcontr
M3
M5
Current starv
B.Supmonchai
Current-Starved Inverter Simulation

tpH
tpHL
(nsec)
L (nsec)
6
4
2
0.0
0.5
2102-545 Digital ICs
1.5
V co ntr (V)
Vctrl (V)
2.5
Sequential Logic
The device is in the
subthreshold region
when Vctrl is smaller
than VT, resulting in
large variations of tp
as the drive current
is exponentially
dependent on the
propagati
drive voltage
of control
 Delay sensitive to
noise and variation
in Vctrl
76
B.Supmonchai
Differential Delay Element and VCO
- Vo2
in1
+
Vo1
+
-
in2
v1
v2
v3
v4
Vctrl
two stage VCO
delay cell
- Inverting Inputs/Outputs
Oscillator with even number
+ Non-Inverting Inputs/Outputs of stages can be implemented
Differential-type VCO has better immunity to common mode
noise (e.g., supply noise) but consume more power
2102-545 Digital ICs
Sequential Logic
77
B.Supmonchai
2-Stage VCO Simulation
3.0
2.5
V1 V2
V3
V4
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
2.5
3.5
time (ns)
The In-Phase and Quadrature Phase are produced simultaneously
2102-545 Digital ICs
Sequential Logic
78