Transcript Document

DCSL & LVDCSL: A High Fan-in,
High Performance Differential Current
Switch Logic Families
Dinesh Somasekhaar, Kaushik Roy
Presented by
Hazem Awad
Differential Cascade Voltage
Switch Logic
DCVSL is a ratioed logic style that completely
eliminates static currents and provides rail-to-rail
swings.It provides much higher functionality with
greater fan-in than conventional logic. This high
functionality allows the number of logic levels
and gate output nodes to be minimized.
However, DCVSL circuits exhibit high power
consumption due to the pre-charged differential
nature of their outputs.
Differential Current Switch Logic
DCSL is a clocked DCVSL logic style that is
capable of implementing gates with high fan-in.
DCSL achieves low power by restricting internal
voltage swings in the NMOS evaluation tree
without sacrificing speed.
Pre-charged high, Pre-charged low and improved
pre-charged low topologies are possible. Precharged low has superior performance.
Problems with DCSL
Large # of NMOS devices in series forces
high supply to threshold voltage ratios (VDD>>
3Vth). Not applicable in current CMOS
processes.
Steep output spikes are observed.
Gate is not robust due to its sensitivity to
differences in output loading.
LVDCSL was conceived to solve these
problems.
Low Voltage Differential Current
Switch Logic
New topology uses a pre-discharged NMOS
tree with a sensing stage to determine
outputs.
Avoids the problem of output spikes by
having devices P3 & P4 active at start of
evaluation. The strong drive at outputs limits
the glitch.
At the start of evaluation, both T3 & T4 are
off, hence the entire discharge current flows
into the NMOS tree => increased gate
robustness.
LVDCSL operation
The operation of LVDCSL can be divided into
three stages:
A) Pre-charge State (CLK# going high and
CLK low).
B) Evaluate State (CLK going high and CLK#
low)
C) Stable Outputs state (CLK high, CLK#
low)
LVDCSL Operation: Pre-Charge State
CLK # goes high, CLK goes low => T5 & T6
turn ON => T5 turns P4 ON, T6 turns P3 ON.
P3 charges up OUT, P4 charges up
OUTBAR.
OUT turns T8 ON, OUTBAR turns T7 ON =>
a path from VDD to NMOS tree is created.
Since T3 & T4 are OFF, no shunting of
current from NMOS tree occurs => ability to
work with VDD ~ 2Vth.
LVDCSL Operation: Evaluate State
CLK goes high, CLK# goes low =>T1 & T2
turn ON => NMOS tree charges up through
T1 & T7, T2 & T8
Assuming NMOS tree has stronger Path on
left, node A will be held @ lower voltage than
B.
As VB goes > Vth => T3 turns ON => +ve
feedback loop drives OUT low and OUTBAR
high.
T8 turns OFF => NMOS tree disconnected
LVDCSL Operation: Stable Outputs
State
CLK remains high, CLK# remains low.
NMOS tree remains disconnected from
OUTBAR => input changes have no effect on
OUTBAR.
All inputs to gate may be pre-charged at this
state (after evaluation) => allows construction
of simple pipe-lining configuration.
Performance comparison w.r.t.
Domino logic
A 64-bit Carry-Look-Ahead (CLA) adder in
0.35 CMOS was used. VDD = 2.2V, Vth ~
0.45V.
Critical path in adder is an 8-bit building block
composed of two 4-input propagate-generate
Domino gates followed by 2 input static
CMOS.
Domino Delay (not including static gates) was
210 p.s..
LVDCSL implemented critical path in a single
Cont. Performance comparison
w.r.t. Domino Logic
LVDCSL requires a setup time (100ps) unlike
Domino but still manages a delay of 0.33ns
compared to 0.55ns in Domino => 40%
improvement
Domino consumed 8mA current during precharge state. LVDCSL consumed 4.1mA
current during both pre-charge and
evaluation states.
Overall current consumption of LVDCSL is
0.873mA compared to 1.131mA in Domino =>
22% improvement.
Reasons for improved
performance
Higher functionality of LVDCSL allows the two
4-input Domino stages to be combined into
one single 8-input stage (not always possible
though)
Shorter delays are possible in single LVDCSL
stages as opposed to multiple Domino
stages.
LVDCSL has much lighter loading @ gate
inputs because the NMOS transistors in
evaluation tree are small. Also helps with
power consumption.
Conclusion: Features and
shortcomings of LVDCSL
LVDCSL features:
1. High Performance with large stack height
in NMOS tree.
2. Robust gate in spite of use of cross
coupled inverter loop (unlike DCSL). Load
mismatches @ output up to a factor of 5 are
tolerated.
3. Power consumption is limited by
decreasing the voltage swings at internal
nodes of NMOS tree.
Cont. Conclusion: Features and
shortcomings of LVDCSL
4. Latching output stage which automatically
locks out gate inputs once evaluation is
complete.
LVDCSL Shortcomings:
1. High complexity of output stage prevents
its use in simple gates. Layout of output
stage critical because internal nodes A & B
have to be balanced. Very short cycle times
not possible.
2. Does require a setup time w.r.t.
References
1. Dinesh Somasekhar, Kaushik Roy,
“Differential Current Switch logic: A low power
DCVS logic family”, IEEE J. Solid State
Circuits, June 1996.
2. Dinesh Somasekhar, Kaushik Roy,
“LVDCSL: A High Fan-in, High performance
Low Voltage Differential Current Switch logic
family”, TVLSI, Dec 1997.