Transcript 2102-282 Digital Electronics - IC Design & Application Research Lab.

Chapter 6
Dynamic CMOS Circuits
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
August 15, 2004; Revised - July 4, 2005
B.Supmonchai
Goals of This Chapter

In-depth discussion of CMOS logic families
 Static and Dynamic
 Pass-Transistor
 Nonratioed and Ratioed Logic

Optimizing gate metrics
 Area, Speed, Energy or Robustness

High Performance circuit-design techniques
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Dynamic CMOS

In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of N requires 2N devices

Dynamic circuits rely on the temporary storage
of signal values on the capacitance of high
impedance nodes.
 requires only N + 2 transistors
 takes a sequence of precharge and conditional
evaluation phases to realize logic functions
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Dynamic Gate
CLK
Mp
CLK
Mp
on
off
Out
In1
In2
In3
CL
PDN
1
Out
!((A&B)|C)
A
C
B
Me
CLK
CLK
Me
off
on
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
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Conditions on Output

Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.

Inputs to the gate can make at most one transition
during evaluation.

Output can be in high impedance state during and
after evaluation (PDN off), state is stored on CL
 This behavior is fundamentally different than the static
counterpart that always has a low resistance path
between the output and one of the power rails
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Properties of Dynamic Gates

Number of transistors is N + 2 (versus 2N for static
complementary CMOS)
 Logic function is implemented by the PDN only
 Should be smaller in area than static complementary CMOS

Full swing outputs (VOL = GND and VOH = VDD)

Nonratioed - sizing of the devices is not important for
proper functioning (only for performance)

Low noise margin (NML)
 PDN starts to work as soon as the input signals exceed VTn, so
set VM, VIH and VIL all equal to VTn
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Properties of Dynamic Gates II

Faster switching speeds
 Reduced load capacitance due to lower number of transistors
per gate (Cint) so a reduced logical effort
 Reduced load capacitance due to smaller fan-out (Cext)
 No Isc, so all the current provided by PDN goes into
discharging CL
 Ignoring the influence of precharge time on the switching
speed of the gate, tpLH = 0 but the presence of the evaluation
transistor slows down the tpHL

Needs a precharge/evaluate clock
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Properties of Dynamic Gates III

Power dissipation should be better than CMOS
 Consumes only dynamic power – no short circuit power
consumption since the pull-up path is not on when evaluating
 Lower CL- both Cint (since there are fewer transistors
connected to the drain output) and Cext (since there the output
load is one per connected gate, not two)
 No glitches - By construction can have at most one transition
per cycle

However overall power dissipation is usually higher
than static CMOS due to
 higher transition probabilities
 extra load on CLK
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Dynamic Behavior
Evaluate
2.5
CLK
Out
In1
1.5
In2
In3
In &
CLK
0.5
In4
Out
Precharge
-0.5
CLK
0
0.5
1
Time (ns)
all data inputs set to 1
#Trs
VOH
VOL
VM
NMH
NML
tpHL
tpLH
tp
6
2.5V
0V
VTn
2.5-VTn
VTn
110ps
0ns
83ps
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Notes on Dynamic Behavior

The precharge time is determined by the time it takes to
charge CL through the PMOS precharge transistor.
 Often, the overall digital system can be designed in such a way
that the precharge time coincides with other system functions
(e.g., precharge of a FU can coincide with instruction decode).


The duration of the precharge cycle can be adjusted by
changing the size of the PMOS precharge transistor.
But making it too large increases the gate’s Cint as well
as increasing the capacitive load on the clock.
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Gate Parameters are Time Independent

The amount by which the output voltage drops is a
strong function of the input voltage and the available
evaluation time.
 Noise needed to corrupt the signal has to be larger if the
evaluation time is short – i.e., the switching threshold is truly
time independent.
CLK
Voltage (V)
2.5
Vout (VG=0.45)
1.5
Vout (VG=0.5)
0.5
Vout (VG=0.55)
-0.5
0
20
40
60
80
100
Time (ns)
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Power Consumption of Dynamic Gate
CLK
Mp
Out
In1
In2
In3
CL
PDN
CLK
Me
Eliminates
Static power
Consumption
Power only dissipated when previous Out = 0
But what about clock power impact?
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Dynamic PC is Data Dependent
Dynamic 2-input NOR Gate
A
B
Out
0
0
1
0
1
0
1
0
0
1
1
0
Assume signal probabilities
PA=1 = 1/2
PB=1 = 1/2
Then transition probability
P01 = Pout=0 x Pout=1
= 3/4 x 1 = 3/4
Switching activity can be higher in dynamic gates!
P01 = Pout=0
(static NOR gate P01 = 3/16)
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Issues in Dynamic Design 1:
Charge Leakage
CLK
4
CLK
Mp
3
Out
1
CL
A=0
2
CLK
Me
Evaluate
VOut
Precharge
Leakage sources
Minimum clock rate of a few kHz
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Source of Charge Leakage

Charge stored on CL will leak away with time (input in
low state during evaluation)

Dominant leakage sources are reverse-biased diode (1)
and the sub-threshold leakage (2) of the NMOS
pulldown device.

PMOS precharge device also contributes some leakage
due to reverse bias diode (3) and subthreshold
conduction (4) that, to some extent, offsets the leakage
due to the pull down paths.

Requires a minimum clock rate
 Not good for low performance products such as watches (or
when there are conditional clocks)
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Impact of Charge Leakage

Output settles to an intermediate voltage determined by a
resistive divider of the pull-up and pull-down networks
 Once the output drops below the switching threshold of the
fan-out logic gate, the output is interpreted as a low voltage.
CLK
Voltage (V)
2.5
Out
1.5
0.5
-0.5
0
20
40
Time (ms)
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A Solution to Charge Leakage

Keeper compensates for the charge lost due to the pulldown leakage paths.
Keeper
CLK
A
CL
B
CLK
Same approach as
level restorer logic
Mp Mkp
Me
Out
State
PDN
Out
Mkp
Precharge
Irr.
VDD
ON
OFF
VDD
ON
ON
VDD  0
ON  OFF
Evaluate
If PDN is on, there is a fight between the PDN and the PUN - circuit
must be ratioed so that PDN wins, eventually
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Issues in Dynamic Design 2:
CLK
Mp
Out
A
CL
B=0
CLK
Ca
Me
Cb
Charge Sharing
Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
static power consumption by
downstream gates and
possible circuit malfunction.
When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is
large enough to be below the switching threshold of
the gate it drives causing a malfunction.
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Charge Sharing Example
What is the worst case voltage drop on y? (Assume all inputs are
low during precharge and that all internal nodes are initially at 0V.)
CLK
a
Ca=15fF
B
Cc=15fF
c
A
y=ABC
!A
Load
inverter
Cy=50fF
b
!B
B
!C
C
CLK
!B
d
Cb=15fF
Cd=10fF
Vout = - VDD [(Ca + Cc)/((Ca + Cc) + Cy)]
= - 2.5V*(30/(30+50)) = -0.94V
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Notes on Charge Sharing Example

Output stays high for 4 out of 8 cases (!A B C,
!A !B !C, A !B C, and A B !C)

Worst case is obtained by exposing the
maximum amount of internal capacitance to
the output node during evaluation.
 This happens when !A B C or A !B C

∆V = -0.94 V so the output drops to 2.5 - 0.94 =
1.56 V which is below the switching threshold of
the Load inverter.
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Solution to Charge Redistribution
CLK
Mp Mkp
CLK
Out
A
B
CLK
Me
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
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Issues in Dynamic Design 3:

Backgate Coupling
Susceptible to crosstalk due to 1) high impedance of the
output node and 2) capacitive coupling
CLK
Mp
M6 M5
Out1 =1
Out2 =0
A=0
M1
B=0
M2
CLK
M4
CL1
Me
CL2
M3
In
Static NAND
Dynamic NAND
Out2 capacitively couples with Out1
through the gate-source and gate-drain capacitances of M4
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Backgate Coupling Effect

Capacitive coupling means Out1 drops significantly so
Out2 does not go all the way to ground
3
2
Out1
1
CLK
0
In
Out2
-1
0
2
4
6
Time (ns)
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Notes on Backgate Coupling Effect

The high impedance of the output node makes
the circuit very sensitive to crosstalk effects.
 A wire routed over or next to a dynamic node may
couple capacitively and destroy the state of the
floating node.

Due to capacitive backgate coupling between the
internal and output node of the static gate and
the output of the dynamic gate, Out1 voltage is
reduced.

Out1 overshoots VDD (2.5V) due to clock
feedthrough
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Issues in Dynamic Design 4:

Clock Feedthrough
A special case of capacitive coupling between the clock
input of the precharge transistor and the dynamic output
node
CLK
Mp
Out
A
CL
B
CLK
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Coupling between Out and
CLK input of the precharge
device due to the gate- drain
capacitance. So voltage of
Out can rise above VDD. The
fast rising (and falling edges)
of the clock couple to Out.
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Clock Feedthrough Example
Clock
feedthrough
CLK
Out
2.5
In1
In2
In3
1.5
0.5
Out
In4
CLK
Clock
feedthrough
In &
CLK
-0.5
0
0.5
1
Time (ns)
Signal levels can rise enough above VDD that the normally reversebiased junction diodes become forward-biased causing electrons
to be injected into the substrate.
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Cascading Dynamic Gates
V
CLK
Mp CLK
Out1
Out2
In
CLK
Me CLK
CLK
Mp
In
Out1
Me
VTn
V
Out2
t
Only a single 0  1 transition allowed at the
inputs during the evaluation period!
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Domino Logic
CLK
Mp
11
10
In1
In2
In3
CLK
PDN
Me
Mp Mkp
CLK
Out1
Out2
00
01
In2
In3
PDN
CLK
Me
Assume all inputs to the Domino gate are initially zero
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Why Domino?
CLK
In1
Ini
Inj
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Ini
Inj
PDN
CLK
Like falling dominos!
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Notes on Dominic Logic

Ensures all inputs to the Domino gate are set to 0 at the
end of the precharge period. Hence, the only possible
transition during evaluation is 0 to 1

Additional advantage is that the fan-out of the gate is
driven by a static inverter with a low-impedance output
that increases the noise immunity.

The buffer also reduces the capacitance of the dynamic
output node by separating internal and load
capacitances.

Finally, the inverter can be used to drive a bleeder to
combat leakage and charge redistribution.
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Domino Manchester Carry Chain
CLK
Ci,0
CLK
!(G0 + P0 Ci,0)
3
P0
3
P1
3
3
3
P2
2
P3
3
4
5 G0
1
Ci,4
4 G1
3 G2
2 G3
1
6
5
4
3
2
!(G1 + P1G0 + P1P0 Ci,0)
Automatically forms all the intermediate carries
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Domino Comparator
CLK
A3
A2
A1
A0
Out
B3
B2
B1
B0
Don’t need isolation NMOS in the pull-down,
since the PDN is forced off during precharge.
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Properties of Domino Logic

Only non-inverting logic can be implemented, fixes
include
 can reorganize the logic using Boolean transformations
 use differential logic (dual rail)
 use np-CMOS (zipper)

Very high speed
 tpHL = 0, only Low-High transitions allow
 static inverter can be optimized to match fan-out (separation of
fan-in and fan-out capacitances)
 Input capacitances reduced - smaller logical effort
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Differential (Dual Rail) Domino

Solve problem of non-inverting logic
off
CLK
Out = AB 1
Mp
on
Mkp
Mkp
0
CLK
Mp
1
0 !Out = !(AB)
A
!A
!B
B
CLK
Me
AND/NAND
Due to its high-performance, differential domino is very popular
and is used in several commercial microprocessors!
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Notes on Differential Domino

The inputs and their complements come from other
differential DR gates and thus all inputs are low during
precharge and make a conditional transition from 0 to 1.

Expensive - but can implement any arbitrary function.

Use significant power since they have a guaranteed
transition every single clock cycle (regardless of signal
statistics, since either Out or !Out will transit from 0 to 1).

Nonratioed (even though it has a cross-coupled PMOS
pair)
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np-CMOS (Zipper)
CLK
In1
In2
In3
CLK
!CLK
Mp
11
10
PDN
Me
Out1
In4
In5
PUN
00
01
Me
!CLK
Mp
Out2
(to PDN)
In4 and In5 must be from PDN
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
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NORA (No Race)
CLK
In1
In2
In3
CLK
!CLK
Mp
11
10
Me
Out1
In4
In5
PDN
PUN
00
01
!CLK
Me
Mp
to other
PDN’s
Out2
(to PDN)
to other
PUN’s
Very sensitive to Noise!
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Note on np-CMOS and NORA


DEC alpha uses np-CMOS logic (Dobberpuhl)
Have to size the PUN’s to equalize the delay to that of
the PDN’s

Really dense layouts and very high speed (20% faster
than domino with the correct sizing)

Reduced noise margin (as with any dynamic gate)
 More sensitive to noise

Increase complexity
 Have two clock signals to generate and route - CLK and !CLK
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np-CMOS Adder Circuit
!CLK
!A1
!B1
1x
0x
!B1
!A1
!A1
0  xC
!CLK
!B1
1x
CLK
!C1
2
Sum1
!C1
!A1
!B1
CLK
!CLK
CLK
1  x!C1
0x
A0
C0
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B0
B0
A0
B0
C0
1x
CLK
!CLK
Dynamic CMOS Gates
B0
A0
C0
!Sum0
0x
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How to Choose a Logic Style

Must consider ease of design, robustness (noise
immunity), area, speed, power, system clocking
requirements, fan-out, functionality, ease of testing
4-input NAND
Style
# Trans
Ease
Ratioed? Delay Power
Comp Static
8
1
no
3
1
CPL*
12 + 2
2
no
4
3
domino
6+2
4
no
2
2 + clk
DCVSL*
10
3
yes
1
4
* Dual Rail

Current trend is towards an increased use of
complementary static CMOS: design support through
DA tools, robust, more amenable to voltage scaling.
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