Transcript Combinational MOS Logic Circuit

Combinational MOS Logic
Circuit
A. Marzuki
Topics
• Static Characteristic
• Dynamic Characteristic
• Stick Diagram
Two-Input NOR Gate
VGS,load = 0 V
VOL
k = μCox W/L
for case either Driver are ON,
!VGS = VOH
for case both Driver are ON,
CMOS NOR GATE
Analysis similar to CMOS Inverter , VOL = 0 V,
VOH=VDD
A
!VS4=VDD-VSD3
!ID3+ID4=2ID
B
!replace ID of B with A
CMOS TG
!Vout is varied.
!see current direction for
Source terminal indication
CMOS TG
EXAMPLE
Complex Logic Circuits
•OR by parallelconnected drivers.
•AND by seriesconnected drivers.
•Inversion by MOS
circuit operation.
CMOS Logic Circuit
Pull up graph: vertex is drawn with area
of pull down graph. Edge cross pull down
graph’s edge once.
Pull down graph (NMOS)
Vertex represents
node
Equivalency
PMOS Gate length
increase, NMOS Gate
width increase
CMOS NOR Gate
Discuss Example 7.2
Assuming W/L for PMOS is 15 for NMOS is 10
Answer is W/L for n is 12, while p is 12.5
Dynamic Characteristics (Delay)
Capacitance? Pls read chapter 6 and chapter 3. For our case, We just
Use Cout i.e. the final total capacitance.
Propagation Delay
Equivalency
Chapter Six
Stick Diagram
• A stick diagram is a graphical view of a
layout.
• Does show all components/vias (except
possibly tub ties), relative placement.
• Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub
boundaries.
Stick Diagram
• Represents relative positions of transistors
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD
VDD
Inverter
NAND2
Out
Out
In
GND
GND
A B
Common Euler Path
The Euler path is defined as an uninterrupted path
that traverses each edge (branch) of the graph exactly once
Comparison
References
• S-M. Kang and Y. Leblebici ,CMOS Digital
Integrated Circuits: Analysis and Design,,
3rd edition
• Jan M. Rabaey, Anantha Chandrakasan,
and Borivoje Nikolic, Digital Integrated
Circuits: A Design Perspective, 2nd
edition, Prentice Hall, 2002.