Transcript Slide 1
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 Lecture 02: CMOS Logic • Last time: • What is a VLSI system? • What is a VLSI system composed of? How many? • The life cycle of IC design • Topics covered in the class • Today: • Simple descriptions of nMOS and pMOS transistors • How to build logic gates from these devices? Impact of doping on silicon resistivity silicon 4.9951022 atoms in cm3 Resistivity 3.2 105 Ωcm dope with phosphorous or arsenic n-type 1 atom in billion 88.6 Ωcm 1 atom in million 0.114 Ωcm 1 atom in thousand 0.00174 Ωcm dope with boron p-type 1 atom in billion 266.14 Ωcm 1 atom in million 0.344 Ωcm 1 atom in thousand 0.00233 Ωcm Electrons are more mobile/faster than holes What happens if we sandwich p & n types? A p n B One-dimensional representation Al More sandwiches: nMOS transistor Source Gate Drain Polysilicon SiO2 n+ n+ p g=0: When the gate is at a low voltage (VGS < VT): p-type body is at low voltage source and drain-junctions diodes are OFF transistor is OFF, no current flows g=1: When the gate is at a high voltage (VGS ≥ VT): negative charge attracted to body inverts a channel under gate to n-type transistor ON, current flows bulk Si nMOS pass ‘0’ more strongly than ‘1’ Source Gate Drain Polysilicon SiO2 n+ n+ p • Why does ‘1’ pass degraded? bulk Si More sandwiches: pMOS transistor Source Gate Drain Polysilicon SiO2 p+ p+ n g=0: When the gate is at a low voltage (VSG < VT): positive charge attracted to body inverts a channel under gate to p-type transistor ON, current flows g=1: When the gate is at a high voltage (VSG ≥ VT): negative charge attracted to body source and drain junctions are OFF transistor OFF, no current flows bulk Si pMOS pass ‘1’ more strongly than ‘0’ Source Gate Drain Polysilicon SiO2 p+ p+ n • Why does ‘0’ pass degraded? bulk Si An nMOS and pMOS make up an inverter pMOS + nMOS = CMOS More CMOS gates B A B F = AB 0 What is this gate function? What’s wrong about this design? 3-input NANDs Series-Parallel Combinations What are the transistor schematics of the NOR gate? AOI Transmission gate MUX Latch design Flip-flop (edge triggered) design Summary • We studied CMOS gate structure but we do not know they get fabricated or how fast they are • Next time: CMOS fabrication