Transcript Digital Logic Design - University of Tehran

Digital Logic Design
Lecture # 6
University of Tehran
Outline
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Review of Lecture # 5
Logic Values
Verilog
Gate’s Fan-out Limitation
More on Minimization by KM
Review of Lecture # 5
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In the last session, we talked about timing issues in
circuits, as we observed, the matters are not only
based on the delay of change of the actual signals
but also on the propagation of the gates.
We considered 2 delay times, trise and tfall, for the
signals, the first being the time needed for a signal to
reach 90% of its total value from the instance it had
10% of that value and the second the time for
transition from 90% to 10% of its total value. We
also talked of tPHL and tPLH.
Review of Lecture # 5
(continued…)
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As we observed different levels of abstractions were
able to satisfy our needs in circuit timing, but as we
went higher in the levels of abstraction, more details
and features of the real world were ignored.
Logic Values
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So far we have been using a logic value system with
only 2 values -0 and 1. This system causes some
problems of different nature. Some of these
problems can occur in some of the approaches used
for circuit timing, others are for instance problems of
representation of certain states such as:
0
1
?
What value -0 or 1- can
represent this state?
Logic Values (continued…)
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These problems originate from the fact that we have
no accurate control on the switching of transistors
used in our circuits.
A state such as the one shown in the example in the
last slide where the wire is float, is represented by
the value ‘Z’ and is called high-impedance.
Another state occur when a wire has a value between
0 and 1 or it has an unknown value. This state is
represented by the value ‘X’.
Logic Values (continued…)
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If we, for instance, consider a not structure,
supposing certain delay times for the PMOS and
NMOS transistors can cause a Z or X to be seen on
the output at certain instances of times.
vdd
1
0
Logic Values (continued…)
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As a result of the mentioned problems of the 2 state
logic system, we will be using a 4 value logic system
from now on (0-1-Z-X).
Note: NMOS transistors work faster than PMOS
transistors of the same size, due to the higher
mobility of electrons (in NMOS transistors) in
comparison to the mobility of holes (in the PMOS
transistors). Hence it would be preferable to use
larger NMOS transistors in our structures, but this
would cause problems in lay-out making the use of
differently sized transistors not so practical.
Verilog
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Observation of different states that can occur in
circuit timing become rather complex to do by hand,
thus we use a Hardware Description Language such
as Verilog for this means.
Until now we have seen different representation for
our circuits (transistors-gates-truth tables etc). If
analysis of a circuit is to be done by a computer, we
have to somehow represent our circuit to the
computer. Verilog is a language used for this
representation.
Verilog (continued…)
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The Verilog is a 4 value logic system that can
describe circuits in different levels of abstraction, for
instance:
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Transistor level
Gate level
RTL
Behavioral
We can also specify timings for our descriptions.
Verilog (continued…)
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Example: We want to specify a CMOS nand gate in
verilog:
module cmosnand(a, b, w);
vdd
input a, b;
output w;
w
supply1 vdd;
a
supply0 gnd;
b
im1
wire im1;
nmos #(2, 3, 4)(im1, gnd, b);
nmos #(2, 3, 4)(w, im1, a);
pmos #(3, 4, 5)(w, vdd, b);
pmos #(3, 4, 5)(w, vdd, a);
endmodule
Verilog (continued…)
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We will now talk a little about the structures used in
our sample Verilog program. About the description of
the NMOS and PMOS transistors it must be
mentioned that there is no need to be concerned
about the order in which the transistors are
described. This is due to the concurrency of different
sections of a circuit described in Verilog. The 3
number in given parentheses after the number sign
are delay times of the specific transistor which are in
order from left to right transition to 1, 0 and Z times.
If these delay times were not mentioned, sharp
transitions to different values would have been used.
Verilog (continued…)
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Also the output, the input and the control of the
transistor must be mentioned in order from left to
right in the next parentheses.
Example:
We want to see how the delays show themselves
in the following example where the input of a not
gate changes from 0 to 1.
vdd
0
1
5ns
3ns
Verilog (continued…)
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Answer: When the input of the not gate changes
from 0 to 1, it takes 3ns for a 0 to be put on the
output from the NMOS transistor, while it takes 5ns for
the PMOS transistor to go to the Z state. Thus in the
2ns interval, the output of the gate will become X.
When the input of the not gate changes again from 1
to 0, it takes 3ns for a 1 to be placed alongside the 0
on the output, and takes 4ns for the NMOS to turn to
Z. Again in a 1ns interval, an X will be derived on the
output. The output of the not gate will look
something like the following figure:
2ns
1ns
Verilog (continued…)
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Turning back to Verilog, we can also point out a scale
and precision for the delays we give in the following
format:
`timescale 1ns/100ps
Verilog (continued…)
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Testing the module we have constructed in Verilog is
done by composing a test bench. The following code
is a test bench for the CMOS nand module we wrote
before:
module testnand();
reg ai, bi;
wire wo;
cmosnand n1(ai, bi, wo);
initial begin
ai=0; bi=1;
#25 ai=1;
#30 bi=0;
end
endmodule
Verilog (continued…)
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In the initial block we are able to give the inputs
certain values at certain times.
Gate’s Fan-out Limitation
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When a gate’s output is used to drive another gate, a
capacitance is put ahead of the driving gate. A
matter of importance is how many gates a gate is
able to drive with consideration of the above
mentioned. This limitation is a result of the inner
specification of the gate.
We consider the gates that are to be droved uniform.
This is because different gates may need different
current to be droved with, making the analysis of
such situations even more complex. This fan-out
limitation used for a gate is another level of
abstraction used to hide details.
More on Minimization by KM
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When constructing a minimal SOP form, we first look
for the EPI’s in a set of PI’s. In this map our EPI’s
would be cd, ad c , each essential because of the
marked boxes in the map. In order to cover the
remaining uncovered ones, we can include either the
prime implicant abc or abd which shows us that the
minimal SOP isn’t unique. ab 00 01
10
11
cd
00
01
1 *
1
0
4
1
5
12
8
13
9
1
3
7
15
* 1
11
2
6
14
10
1 *
11
1
1 *
10
More on Minimization by KM
(continued…)
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Thus the minimal SOP form could be abc  cd  ad c
which gives us a two level and/or logic network, as
shown below:
c
d
a
d
c
a
b
c
More on Minimization by KM
(continued…)
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For a minimal POS form we would have. As can be
seen, in this example the minimal POS form is unique
whereas the minimal SOP form is not.
ab
00
01
10
11
c
cd
d
0
0
00
0
01
4
12
1
5
13
9
3
7
15
11
* 0
* 8 *
0 *
0
a
c
11
10
2
0 *
6
0 *
14
0*
* 0
10
(c  d )(a  c)(b  c  d )
d
c
b
More on Minimization by KM
(continued…)
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Now we will examine a 5 variable map which is
actually shown as two 4 variable maps alongside
each other.
ab
cd
00
01
00
0
1
1
01
10
11
4
12
5
13
9
1
11
1
1
3
7
15
11
2
6
14
10
cd
00
8
1
ab
10
01
00
0
1
1
01
10
11
4
12
5
13
8
1
9
1
11
1
3
7
15
11
2
6
14
10
10
a=0
abcde + abcde = bcde
a=1
abe+abe=be
1
More on Minimization by KM
(continued…)
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Consider two 1’s placed in the map as shown in blue.
These two terms would be represented as abcde and
abcde . Obviously these two terms are boolean
adjacent so are the implicants shown in green which
are abe and abe . As a result we need to change our
definition of physical adjacency in such maps and
consider the two 4 variable maps as two maps
stacked onto each other, so that situations such as
the above mentioned can be dealt with accordingly
and the combinations of the adjacent terms
mentioned done on the karnaugh map itself.