Transcript Introduction to Assembly Language

Introduction to Verilog
COE 203
Digital Logic Laboratory
Dr. Aiman El-Maleh
College of Computer Sciences and Engineering
King Fahd University of Petroleum and Minerals
Outline …
 Introduction
 Why use HDL?
 Definition of Module
 Gate Level Modeling
 Verilog Primitives
 A Full Adder
 4-bit Adder
 Continuous Assignments
 Behavioral Description of an Adder
 Verilog Operators
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 2
… Outline
 Verilog Logic Values
 Verilog Data Types
 Always Block
 Wire vs. Reg
 If Statements
 Case Statements
 Sequential Circuits
 Generalized Verilog Mealy Model
 Generalized Verilog Moore Model
 Finite State Machine Example
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 3
Introduction
 Verilog is one of the hardware description languages
(HDL) available in the industry for hardware designing.
 It allows designers to design at Behavior Level, Register
Transfer Level (RTL), Gate level and at switch level.
 Parallel not serial (Not like C language).
 Verilog can describe everything from single gate to full
computer system.
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 4
Why use HDL ?
 Digital systems are highly complex;
millions of transistors.
 For large digital systems, gate-level
design is very difficult to achieve in
a short time.
 Verilog allows hardware designers
to express their designs with
behavioral constructs, deferring the
details of implementation to a later  © Intel P4 Processor
 Introduced in 2000
stage in the final design.
 Computer-aided design tools aid in
the design process.
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
 40 Million Transistors
 1.5GHz Clock
slide 5
Definition of Module
 The <module name> is an
identifier that uniquely
names the module.
 The <port list> is a list of
input, inout and output ports
which are used to connect
to other modules.
 Interface: port and
parameter declaration
 Body: Internal part of
module
 Add-ons (optional)
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 6
The Module Interface …
Port List
Port Declaration
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 7
… The Module Interface
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 8
Gate Level Modeling
 Net-list description
 built-in primitives gates
IN1
OUT1
X
IN2
module my_gate(OUT1, IN1, IN2);
output OUT1;
Internal Signal
input IN1, IN2;
wire X;
Any internal net must be defined as wire
and (X, IN1, IN2);
not (OUT1, X);
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 9
Verilog Primitives
 Basic logic gates only
 and
 or
 not
 buf
 xor
 nand
 nor
 xnor
 bufif1, bufif0
 notif1, notif0
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 10
Primitive Pins Are Expandable
nand (y, in1, in2) ;
nand (y, in1, in2, in3) ;
nand (y, in1, in2, in3, in4) ;
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 11
A Half Adder
module hadd (S, C, X, Y);
input X, Y;
output S, C;
xor (S, X, Y);
and (C, X, Y);
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
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A Full Adder
module fadd (co, s, a, b, c);
input a, b ,c ;
output co, s ;
wire n1, n2, n3;
xor (n1, a, b) ;
xor (s, n1, c) ;
nand (n2, a, b) ;
nand (n3,n1, c) ;
nand (co, n3,n2) ;
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 13
Instantiation of Modules
module fadd (S, C, X, Y, Z);
input X, Y, Z;
output S, C;
w1
wire w1, w2, w3;
hadd M1 (w1, w2, X, Y);
w2
w3
hadd M2 (S, w3, w1, Z);
or (C, w2, w3);
endmodule
 Here we instantiate hadd twice. i.e., placing two hadd circuits and
connecting them.
 This full adder is built from two half adders and an OR gate.
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 14
4-bit Adder
module add4 (s,cout,ci,a,b);
input [3:0] a,b ;
// port declarations
input ci ;
output [3:0] s ;
output cout ;
a[3] b[3]
// vector
cout
wire [2:0] co ;
a[2] b[2] a[1] b[1] a[0] b[0]
a3
a2
co[2]
s[3]
a1
co[1]
s[2]
a0
co[0]
s[1]
s[0]
fadd a0 (co[0], s[0], a[0], b[0], ci) ;
fadd a1 (co[1], s[1], a[1], b[1], co[0]) ;
fadd a2 (co[2], s[2], a[2], b[2], co[1]) ;
fadd a3 (cout, s[3], a[3], b[3], co[2]) ;
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 15
ci
Continuous Assignments
 Describe combinational logic
 Operands + operators
 Drive values to a net
 assign out = a&b ;
// and gate
 assign eq = (a==b) ;
// comparator
 wire #10 inv = ~in ;
// inverter with delay
 wire [7:0] c = a+b ;
// 8-bit adder
 Avoid logic loops
 assign a = b + a ;
 asynchronous design
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 16
Simple XOR Gate
module my_xor( C, A, B );
output C;
input A, B;
assign C = (A ^ B);
endmodule
Introduction to Verilog
Operation Operator
~
Bitwise NOT
&
Bitwise AND
|
Bitwise OR
^
Bitwise XOR
COE 203 – Digital Design Lab – KFUPM
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Full Adder
module fadd (S, Cout, A, B, Cin);
output S, Cout;
A
input A, B, Cin;
B
S
Cin
assign S = A ^(B ^ Cin);
Cout
assign Cout = (A & B)
| (A & Cin)
| (B & Cin) ;
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 18
Behavioral Description of an Adder
module adder4 ( S, Cout, A, B, Cin);
input [3:0] A, B;
input Cin;
4-bit operands,
5-bit result
output [3:0] S;
output Cout;
{ Cout, S } is a 5 bit bus:
assign { Cout, S } = A + B + Cin;
Cout S[3] S[2] S[1] S[0]
// note: Verilog treats wires as ‘unsigned’ numbers
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 19
Behavioral Description of an Adder
module adder (cout, sum, a, b, cin);
parameter width = 2;
input cin;
input [width:0]
a, b;
output [width:0]
sum;
output cout;
assign {cout, sum} = a + b + cin;
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 20
Verilog Operators
{}
~
bit-wise NOT
&
bit-wise AND
arithmetic
|
bit-wise OR
modulus
^
bit-wise XOR
^~ ~^
bit-wise XNOR
&
reduction AND
|
reduction OR
~&
reduction NAND
~|
reduction NOR
concatenation
+ - * /
%
> >= < <=
relational
!
logical NOT
&&
logical AND
||
logical OR
^
reduction XOR
==
logical equality
~^ ^~
reduction XNOR
!=
logical inequality
<<
shift left
?:
conditional
>>
shift right
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 21
Verilog Logic Values
 The underlying data representation allows for any bit to
have one of four values
 1, 0, x (unknown), z (high impedance)
 x — one of: 1, 0, z, or in the state of change
 z — the high impedance output of a tri-state gate.
 x … not a real value. There is no real gate that drives an
x on to a wire. x is used as a debugging aid.
 x means the simulator can’t determine the answer and
so maybe you should worry!
 All values in a simulation start as x.
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 22
Verilog Data Types
 Nets: wire
 variables represent physical connections between structural entities
such as gates.
 A wire does not store a value.
 Registers: reg
 store the last value that was procedurally assigned to them
 Integers: 4’d3, 4’b0100, 6’h20
 Array: reg [9:0] ram
 Parameter
 parameter word_size = 16
 wire [word_size-1:0] bus;
 Preprocessor Directive
 `define BEQ 4’b0100
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 23
Always Block
 always blocks are procedural blocks that contain sequential statements.
 Syntax
 always @(sensitivity list) begin
……….
end
 sensitivity list prevents the always block from executing again until another
change occurs on a signal in the sensitivity list.
 Level type
 always @(a or b or c)
 Edge type
 always @(posedge clock)
 always @(negedge clock)
 if-else and case statement are only in always block
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 24
Wire vs. Reg
 There are two types of variables in Verilog:
 Wires (all outputs of assign statements must be wires)
 Regs (all outputs of always blocks must be regs)
 Both variables can be used as inputs anywhere
 Can use regs or wires as inputs (RHS) to assign statements
 assign bus = LatchOutput + ImmediateValue
 // bus must be a wire, but LatchOutput can be a reg
 Can use regs or wires as inputs (RHS) in always blocks
 always @ (in or clk)

Introduction to Verilog
if (clk) out = in
// in can be a wire, out must be a reg
COE 203 – Digital Design Lab – KFUPM
slide 25
If Statements
Syntax
if (expression)
begin
...statements...
end
else if (expression)
begin
...statements...
end
...more else if blocks
else
begin
...statements...
end
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
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Case Statements
Syntax
case (expression)
case_choice1:
begin
...statements...
end
case_choice2:
begin
...statements...
end
...more case choices blocks...
default:
begin
...statements...
end
endcase
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 27
Example: Full Adder
module fadd (A, B, Cin, S, Cout);
input A, B, Cin;
output S, Cout;
A
reg S, Cout;
B
S
Cin
always @(A or B or Cin)
begin
S = (A ^ B ^ Cin);
Cout
Cout = (A & B)|(A&Cin)|(B&Cin);
end
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 28
Example: 2x1 Multiplexer
 Method 1
module mux2x1 ( b, c, select, a);
input b, c, select;
output
a;
c
0
b
1
a
SL
assign a = (select ? b : c);
endmodule
 Method 2
select
module mux2x1 ( b, c, select, a);
input b, c, select;
output a; reg a;
always@(select or b or c) begin
if (select) a=b;
else a=c;
end
endmodule
Introduction to Verilog
Method 3
module mux2x1 ( b, c, select, a);
input b, c, select;
output a; reg a;
always@(select or b or c) begin
case (select)
1’b1: a=b;
1’b0: a=c;
endcase
end
endmodule
COE 203 – Digital Design Lab – KFUPM
slide 29
Example: DeMux
module demux ( D, select, y0, y1);
input
D, select;
output y0, y1;
reg
y0, y1;
always @( D or select ) begin
if( select == 1’b0)
begin
y0 = D; y1 = 1’b0;
end
else
begin
y0 = 1’b0; y1 = D;
end
end
endmodule
Introduction to Verilog
D
COE 203 – Digital Design Lab – KFUPM
y0
y1
Select
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Example: Arithmetic Unit
module arithmetic (A, B, Y, Sel);
parameter width=3; input [width-1:0] A, B; input [1:0] Sel;
output [width-1:0] Y; reg [width-1:0] Y;
always @(A or B or Sel) begin
case (Sel[1:0])
2'b 00 : Y = A+B;
2'b 01 : Y = A-B;
2'b 10 : Y = A+1;
2'b 11 : Y = A-1;
default: Y=0;
endcase
end
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 31
Example: Logic Unit
module logic (A, B, Y, Sel);
parameter width=2; input [width-1:0] A, B; input [2:0] Sel;
output [width-1:0] Y; reg [width-1:0] Y;
always @(A or B or Sel) begin
case (Sel[2:0])
3'b 000 : Y = A & B;
// A and B
3'b 001 : Y = A | B;
// A or B
3'b 010 : Y = A ^ B;
// A xor B
3'b 011 : Y = ~A;
// 1’s complement of A
3'b 100 : Y = ~(A & B);
// A nand B
3'b 101 : Y = ~(A | B);
// A nor B
default : Y = 0;
endcase
end
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 32
Sequential Circuits
 Sequential circuits consist of both combinational logic
and storage elements.
 Sequential circuits can be
 Mealy-type: outputs are a combinatorial function of both Current State
signals and primary inputs.
 Moore-type: outputs are a combinatorial function of Current State
signals.
Primary
Inputs
Combinational
Logic
Current State
Introduction to Verilog
Next State
^
CLK
FFs
Primary
Outputs
COE 203 – Digital Design Lab – KFUPM
slide 33
Generalized Verilog Mealy Model
reg Y, D, Z;
always @ (posedge CLK or posedge Reset)
begin: Register
IF (Reset) Y = 0 else Y = D;
end;
always @ (X or Y)
begin: Transitions
D = F1(X, Y);
end;
X
Y
always @ (X or Y)
begin: Output
Z = F2(X, Y);
end;
Introduction to Verilog
Z
F2
F1
Register
D
CLK Reset
COE 203 – Digital Design Lab – KFUPM
slide 34
Generalized Verilog Moore Model
reg Y, D, Z;
always @ (posedge CLK or posedge Reset)
begin: Register
IF (Reset) Y = 0 else Y = D;
end;
always @ (X or Y)
begin: Transitions
D = F1(X, Y);
end;
X
Z
F2
Y
always @ (Y)
begin: Output
Z = F2(Y);
end;
Introduction to Verilog
F1
Register
D
CLK Reset
COE 203 – Digital Design Lab – KFUPM
slide 35
Finite State Machine Example …
1/10
0/01
Reset=0
00
s0
-/10
01
s1
• Mealy model
0/00
10
s2
• Single input, two outputs
1/10
11
s3
• Asynchronous reset
-/10
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 36
… Finite State Machine Example …
module fsm_ex (clk, reset, in, out);
input clk, reset, in;
output [1:0] out;
reg [1:0] out, CS, NS;
parameter s0= 2'b00, s1=2'b01, s2=2'b10, s3=2'b11;
always @ (posedge clk or posedge reset)
begin: Register
if (reset) CS = s0; else CS = NS;
end
always @ (in or CS)
begin: Transitions
case (CS)
s0: if (in) NS = s1; else NS = s2;
s1: if (in) NS = s2; else NS = s1;
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 37
… Finite State Machine Example
s2: NS = s3;
s3: NS = s0;
default: NS = s0;
endcase
end
always @ (in or CS)
begin: Output
case (CS)
s0: if (in) out = 2’b 10; else out = 2’b 00;
s1: if (in) out = 2’b 10; else out = 2’b 01;
s2: out = 2’b 10;
s3: out = 2’b 10;
default: out = 2’b 00;
endcase
end
endmodule
Introduction to Verilog
COE 203 – Digital Design Lab – KFUPM
slide 38