Transcript module

COE 405
Introduction to Logic Design
with Verilog
Dr. Aiman H. El-Maleh
Computer Engineering Department
King Fahd University of Petroleum & Minerals
Outline

Introduction

Definition of a module

Gate-level modeling

Verilog primitives

Verilog Syntax

Verilog Data Types

Module instantiation

Organization of a Testbench for Verifying a Unit Under
Test (UUT)

Propagation, inertial and transport delay

Truth Table Models of Combinational and Sequential
Logic with Verilog
1-2
Introduction

Verilog is one of the hardware description languages
(HDL) available in the industry for hardware designing.

Verilog is a standard HDL (IEEE 1364-1995, 2001, 2005)

It allows designers to design at Behavior Level,
Register Transfer Level (RTL), Gate level and at switch
level.

Parallel not serial (Not like C language).

Verilog can describe everything from single gate to full
computer system.
1-3
Why use HDL ?

Digital systems are highly
complex; millions of transistors.

For large digital systems, gatelevel design is very difficult to
achieve in a short time.

Verilog allows hardware designers
to express their designs with
behavioral constructs, deferring
the details of implementation to a
 © Intel P4 Processor
later stage in the final design.

Computer-aided design tools aid
in the design process.
 Introduced in 2000
 40 Million Transistors
 1.5GHz Clock
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A Verilog Model

A digital system can be described at several levels of
details (more details means more design entry time!):
• Gate-level  Net-list similar to schematic or breadboarding
• Register-transfer-level (RTL): Describing logic between
•

registers using simple assignment statement (two types of
assignments; continuous and procedural)  logic synthesis
tools convert it to gate-level netlist (gates and FFs)
Behavioral description: programming-like structures (if-thenelse, case, loops …etc) to describe what the circuit does (i.e.
behavior) rather than how  requires a high-level synthesis
tool to synthesize an RTL implementation (DP & CU) which
can then be synthesized into gate-level netlist.
A digital system is described as a set of modules 
Basic building block encapsulation
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Definition of a Module

The <module name> is an
identifier that uniquely
names the module.

The <port list> is a list of
input, inout and output ports
which are used to connect
to other modules.

Interface: port and
parameter declaration

Body: Internal part of
module

Add-ons (optional)
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The Module Interface
This is the old Verilog
(Verilog-95)
Port
List
Port
Declaration
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The Module Interface
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Definition of a Module: Verilog-2005

Module & Port Declaration:
module [module-name] #(parameter declarations)
(
[mode] [ data-type] [port-names] ,
[mode] [ data-type] [port-names] ,
...
[mode] [ data-type] [port-names]
);
Mode: input, output or inout
Data-Type: wire, reg or integer (scalar or array)
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Example
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Gate Level Modeling (structural)

Net-list description: built-in primitives gates
An undeclared identifier is treated by default as a wire
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Verilog Primitives for Modeling
Combinational Logic Gates

Verilog has 26 primitives for modeling combinational
logic gates:
• and
• or
• not
• buf
• xor
• nand
• nor
• xnor
• bufif1, bufif0
• notif1, notif0
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Primitive Pins Are Expandable
nand (y, in1, in2);
nand (y, in1, in2, in3);
nand (y, in1, in2, in3, in4);
The output port of a primitive must be the first in
the list of ports.
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Full Adder Model
module fadd (output co, s, input a, b, c);
wire n1, n2, n3;
xor (n1, a, b) ;
xor (s, n1, c) ;
nand (n2, a, b) ;
nand (n3, n1, c) ;
nand (co, n3,n2) ;
endmodule
1-14
Verilog Syntax

Identifiers:
• Composed of letters, digits, the underscore character (_), and
•
•
the dollar sign ($). $ is usually used with a system task or
function
The first character of an identifier must be a letter or
underscore
Verilog is a case-sensitive language D_BUS is different from
D_Bus

Keywords: predefined identifiers that are used to
describe language constructs. E.g. module, always,
wire …etc.  Can not be used as user-defined
identifiers

White space: space, tab, and newline characters are
used to separate identifiers and can be used freely in
the Verilog code
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Verilog Syntax

Comments: two forms; one-line comment starts with //
and multiple-line comment is encapsulated between /*
and */
// T his is a comment
/* This i s comment line 1 .
This i s comment line 2 .
This i s comment line 3 . * /
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Verilog Data Types

Four-valued system:

Two groups of Data Types: net and variable.

Net group:
• 0: for "logic Low, or a false condition
• I: for "logic High", or a true condition
• z: for the high-impedance state
• x: for an unknown value (in simulations)
• Wire: could be 1-bit or array (e.g. wire a; wire [3:0] sum;)
• Wand: wired-and
• supply0
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Verilog Data Types

Variable group: represent abstract storage in
behavioral modeling (The inferred circuit may or may
not contain physical storage components)
• reg: The most commonly used data type in this group
• Integer: explained in next slide

real, time, and realtime: can only be used in modeling
and simulation
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Integer Numbers in Verilog

Constant numbers can be specified in decimal,
hexadecimal, octal, or binary format

Integer numbers can be specified as:
•
Syntax: <size>'<radix><value> (size is in number of bits)
•
•
the first character  so use it for better clarity.
Examples: 12’b1011_1100_0010, ‘hA8, 8’d 15)
When <size> is smaller than <value>, then left-most bits of
<value> are truncated
• Sized or unsized numbers ( Unsized numbers are 32 bits )
• In a radix of binary, octal, decimal, or hexadecimal
• Radix and hex digits (a,b,c,d,e,f) are case insensitive
• Spaces are allowed between the size, radix and value
• The character (_) is legal anywhere in a number except as
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Module Instantiation

Two ways to connect the ports of the instantiated
module to the signals in the instantiating module:
• 1. By name:
[module-name] [instance-name]
(
. [port-name] ( [signal-name] ) ,
.[port-name] ([signal-name]),
);
• 2. By order:
eq1 bit0 (a[0] , b [0] , e0 ) ;
eq1 bitl (a[1] , b [1] , e1 ) ;
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Module Instantiation
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Module Instantiation
module Add_rca_16 (output c_out, output [15:0] sum, input [15:0] a, b, input c_in);
wire c_in4, cin8, c_in12;
Add_rca_4 M1 (c_in4, sum[3:0], a[3:0], b[3:0], c_in);
Add_rca_4 M2 (c_in8, sum[7:4], a[7:4], b[7:4], c_in4);
Add_rca_4 M3 (c_in12, sum[11:8], a[11:8], b[11:8], c_in8);
Add_rca_4 M4 (c_out, sum[15:12], a[15:12], b[15:12], c_in12);
endmodule
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Module Instantiation
module Add_rca_4 (output c_out, output [3:0] sum, input [3:0] a, b, input c_in);
wire c_in2, cin3, c_in3;
Add_full M1 (c_in2, sum[0], a[0], b[0], c_in);
Add_full M2 (c_in3, sum[1], a[1], b[1], c_in2);
Add_full M3 (c_in4, sum[2], a[2], b[2], c_in3);
Add_full M4 (c_out, sum[3], a[3], b[3], c_in4);
endmodule
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Module Instantiation
module Add_full (output c_out, sum, input a, b, c_in);
wire w1, w2, w3;
Add_half M1 (w2, w1, a, b);
Add_half M2 (w3, sum, c_in, w1);
or
M3 (c_out, w2, w3);
endmodule
module Add_half (output c_out, sum, input a, b);
xor
M1 (sum, a, b);
and
M2 (c_out, a, b);
endmodule
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Module Instantiation
module Comp_2_str (output A_gt,_B, A_lt_B, A_eq_B, input A0, A1, B0, B1);
nor (A_gt_B, A_lt_B, A_eq_B);
or (A_lt_B, w1, w2, w3);
and (A_eq_B, w4, w5);
and (w1, w6, B1);
and (w2, w6, w7, B0);
and (w3, w7, B0, B1);
not (w6, A1);
not (w7, A0);
xnor (w4, A1, B1);
xnor (w5, A0, B0);
endmodule
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Module Instantiation
module Comp_4_str (output A_gt,_B, A_lt_B, A_eq_B,
input A3, A2, A1, A0, B3, B2, B1, B0);
wire
w1, w0;
Comp_2_str M1 (A_gt,_B_M1, A_lt_B_M1, A_eq_B_M1, A3, A2, B3, B2);
Comp_2_str M0 (A_gt,_B_M0, A_lt_B_M0, A_eq_B_M0, A1, A0, B1, B0);
or (A_gt_B, A_gt_B_M1, w1);
and (w1, A_eq_B_M1, A_gt_B_M0);
and (A_eq_B, A_eq_B_M1, A_eq_B_M0);
or (A_lt_B, A_lt_B_M1, w0);
and (w0, A_eq_B_M1, A_lt_B_M0);
endmodule
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Test Methodology

Modeling begins with a complex functional unit and
partitions it in a top-down fashion to enable design of
simpler units.

Systematic verification begins with simpler units and
moving to more complex units in design hierarchy.

To verify functionality of a digital circuit build a test
bench that applies stimulus patterns to the circuit and
collect responses.

Responses can be displayed or compared to a correct
response.

Test bench is a separate Verilog module.
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Organization of a Testbench for
Verifying a Unit Under Test (UUT)
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Testbench Example
module t_Add_half();
wire sum, c_out;
reg a, b;
Add_half M1 (c_out, sum, a, b);
initial begin
#100 $finish;
end
initial begin
#10 a=0; b=0;
#10 b=1;
#10 a=1;
#10 b=0;
end
endmodule
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Testbench Example

The keyword initial declares a single-pass behavior
that begins executing when the simulator is activated.

Statements within begin and end block keywords are
called procedural statements.

Procedural statements execute sequentially

# is a delay control operator

A delay control operator preceding procedural
assignment statement suspends its execution and the
execution of subsequent statements for specified
delay time

reg declaration ensures that variables will keep their
value until the next procedural assignment statement

$finish ends simulation
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Testbench Template
module t_DUTB_name(); // substitute the name of the UUT
reg ----; // declaration of register variables for
// primary inputs of the UUT
wire ----; // declaration of primary outputs of UUT
parameter time_out= // provide a value
UUT_name M1 (UUT ports go here);
initial $monitor() // specification of signals to be
// monitored and displayed as text
initial time_out $finish // stopwatch to ensure termination
// of simulation
initial begin
// behavioral statements generating
// wavefroms to input ports
end
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endmodule
Propagation Delay
module Add_full_unit_delay(output c_out, sum, input a, b, c_in);
wire w1, w2, w3;
Add_half_unit_delay M1 (w2, w1, a, b);
Add_half_unit_delay M2 (w3, sum, w1, c_in);
or #1 M3 (c_out, w2, w3);
endmodule
module Add_half_unit_delay (output c_out, sum, input a, b);
xor #1 M1 (sum, a, b);
and #1 M2 (c_out, a, b);
endmodule
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Propagation Delay

To set a certain unit for time units, use the directive
‘timescale

‘timescale 1ns / 1ps directs the simulator to interpret
numerical time variables as having units of
nanoseconds with a resolution of picoseconds
1-33
Inertial Delay

Propagation delay in Verilog obeys inertial delay
model.

Verilog uses the propagation delay of a gate as
minimum width of an input pulse that could affect
output.
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Transport Delay

Propagation delay across a wire is modeled as
transport delay i.e. narrow pulses are not suppressed

Example
• wire #2 A_long_wire declares that A_long_wire has a
transport delay of two time steos.
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Truth Table Models of Combinational
and Sequential Logic with Verilog

Verilog supports truth-table models of combinational
and sequential logic.

A mechanism for building user-defined primitives
(UDPS).

UDPs are delcared in same way as modules with
encapsulation of keywords primitive …endprimitive

The output and inputs of a UDP must be scalar

They can be instantiated just like built-in primitives
with or without propagation delay.
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Truth Table Models of Combinational
and Sequential Logic with Verilog
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Truth Table Models of Combinational
and Sequential Logic with Verilog

The ? Shorthand notation represents iteration of the
table over the values 0, 1, and x in the table i.e., don’t
care on the input
table
//Select
0
0
1
1
?
?
endtable
a
0
1
?
?
0
1
b
?
?
0
1
0
1
:
:
:
:
:
:
:
mux_out
0;
1;
0;
1;
0;
1;
1-38
Truth-table model of a Transparent
Latch

The output of a sequential UDP must be declared to
have type reg
primitive latch_rp (output reg q_out, input enable, data)
// enable
data
state
q_out/next_state
1
1
:
?
:
1;
1
0
:
?
:
0;
0
?
:
?
:
-;
x
0
:
0
:
-;
x
1
:
1
:
-;
1-39
Truth-table model of a D-type flip-flop
1-40