Transcript ece484_1

Introduction to HDLs
• HDL (Hardware Description Language)
• VHDL versus Verilog
• IC world only uses Verilog
How do IC designers use Verilog?
• Can be used for simulation
• Simulation at behavioral level, gate level, and at
the switch level!
• Can be used for circuit synthesis
• Can be used to verify post-synthesis timing
Why Verilog and not VHDL?
• C-like syntax (as opposed to Pascal-like!)
• Better for circuit synthesis
• I feel it is easier to create testbenches but
others will dispute this claim!
• Switch-level descriptions supported
• Timing is more easily included
• Can link in you own C-code!
Verilog Coding Styles
•
•
•
•
Behavioral Descriptions
Dataflow Descriptions
Gate-Level Descriptions (netlist)
Switch-Level Descriptions
Verilog Basics
• Case-sensitive!!!!!
• No special characters in variable names
except _
• Variable names must start with alpha
character
• Free-form
• Very C-like
Concurrent Versus Sequential
• Separate syntax to support descriptions of
concurrent and sequential activity
• Concurrent constructs best for describing
combinational circuits
• Sequential constructs must be used for describing
sequential networks and for writing testbenches …
MAY be used for combinational circuits BUT BE
CAREFUL!
First Example
//
// First example
//
module first_example(f, x, y, z) ;
input x, y, z ;
output f ;
assign f = (x & y & ~z) |
(x & ~y & z) |
(~x & ~y & ~z) ;
endmodule
First Example Testbench
//
// Testbench for first example
//
`timescale 1ns/100ps
module first_example_tb ;
reg
x, y, z ;
wire f ;
integer fid ;
first_example u0(f, x, y, z) ;
initial begin
fid = $fopen("./first_example.out") ;
$fmonitor(fid, $time,
" x = %b, y = %b, z = %b, f = %b", x, y, z, f) ;
#100 x = 1'b0 ; y = 1'b0 ; z = 1'b0 ;
#100 x = 1'b1 ; y = 1'b1 ; z = 1'b0 ;
#100 x = 1'b1 ; y = 1'b1 ; z = 1'b1 ;
#100 $finish ;
end
endmodule
Running Verilog XL
To simulate “first example” do the following:
% verilog first_example_tb.v first_example.v
OR
Create a file called, for example, “modules” and on separate
Lines place the two filenames from above and give the
Command
% verilog –f modules
8-bit Counter
//
// Up-down counter
//
module cnt8bit(cnt, tc, up, down, clr, ld, clk, inp) ;
input up, down, clr, ld, clk ;
input [7:0] inp ;
output tc ;
output [7:0] cnt ;
reg
[7:0] cnt ;
assign tc = (&cnt & up) | (&(~cnt) & down) ;
always @(posedge clk or posedge clr) begin
if (clr)
cnt <= 8'd0 ;
else if (ld)
cnt <= inp ;
else if (up)
cnt <= cnt + 8'd1 ;
else if (down)
cnt <= cnt - 8'd1 ;
else
cnt <= cnt ;
end
endmodule
Testbench for counter
//
// Up-down counter testbench
//
module
reg
reg
wire
wire
cnt8bit_tb ;
clk, clr, up, down, ld ;
[7:0] inp ;
[7:0] cnt ;
tc ;
// Instantiate the counter
cnt8bit uut(cnt, tc, up, down, clr, ld, clk, inp) ;
// Generate the clock
initial begin
$dumpfile("./cnt8bit.dmp") ;
$dumpvars(1, cnt8bit_tb) ;
clk = 1'b0 ;
forever #10 clk = ~clk ;
end
// Test the counter
initial fork
#0 begin
clr = 1'b1 ; up = 1'b0;
down = 1'b0 ;
ld = 1'b0 ; inp = 8'd254 ;
end
#15 begin
clr = 1’b0 ;
ld = 1'b1;
end
#25 begin
ld = 1'b0 ;
up = 1'b1 ;
end
#75 begin
down = 1'b1 ;
up = 1'b0 ;
end
#125 down = 1'b0 ;
#150 $finish ;
join
endmodule
Gate-level description of SR latch
//
// sr latch
// cross-coupled nor gates
//
module sr_latch(q, s, r) ;
output q ;
input s, r ;
wire
qbar ;
nor u0(qbar, s, q) ;
nor u1(q, r, qbar) ;
endmodule
Static CMOS Circuit (Rabaey Text, Chapter 6)
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Static Complementary CMOS
VDD
In1
In2
PUN
InN
In1
In2
InN
PMOS only
F(In1,In2,…InN)
PDN
NMOS only
PUN and PDN are dual logic networks
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
Complementary CMOS Logic Style
Example Gate: NAND
Example Gate: NOR
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
C
Constructing a Complex Gate
VDD
VDD
C
F
SN4
F
SN1
A
SN3
D
B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
Switch-level descriptions of AND and OR gates
// Switch-level OR gate
// Switch-level AND gate
module my_or(z, x, y) ;
module my_and(z, x, y) ;
output z ;
input x, y ;
wire
n1, n2 ;
supply1 vdd ;
supply0 gnd ;
//
pmos
pmos
pmos
nmos
nmos
nmos
d s g
m1(n1, vdd, x) ;
m2(n2, n1, y) ;
m3(z, vdd, n2) ;
m4(n2, gnd, x) ;
m5(n2, gnd, y) ;
m6(z, gnd, n2) ;
endmodule
output z ;
input x, y ;
wire
n1, n2 ;
supply1 vdd ;
supply0 gnd ;
//
pmos
pmos
pmos
nmos
nmos
nmos
d s g
m1(n2, vdd, x) ;
m2(n2, vdd, y) ;
m5(z, vdd, n2) ;
m3(n2, n1, x) ;
m4(n1, gnd, y) ;
m6(z, gnd, n2) ;
endmodule
Testing my_and and my_or
// Test bench for AND and OR gate
module test_and_or ;
wire z_and, z_or ;
reg x, y ;
my_and u0(z_and, x, y) ;
my_or u1(z_or, x, y) ;
initial fork
{x, y}
#20 {x, y}
#30 {x, y}
#40 {x, y}
join
=
=
=
=
2'd0
2'd1
2'd2
2'd3
;
;
;
;
initial begin
$monitor($time, " input is %b z_and is %b z_or is %b", {x, y}, z_and, z_or) ;
end
endmodule