Transcript Lithography

Background
 Process steps up to ‘creating the transistors’ in the
manufacturing Line==> Front End Of Line ==> FEOL
 Connecting the Transistors, capacitors etc ==> BEOL
 Semiconductor
 Band Structure, current carriers, mobility, bias
 MOS device basics
 structure, Operation, depletion, inversion, pinch off
 Issues
 Steps in manufacturing
7/18/2015
2
FEOL: Device
BiPolar Device- Schematic
N
Emitter
P
-
-
+
+
N
N
Base Collector
P
N
Forward Bias
+
-
-
+
N
P
N
Reverse Bias
FEOL: FET Device - Simplified Schematic
Gate
(Base)
Source
(Emitter)
P
P
P
N-Well
Electric
Field of
gate
Gate
Dielectric
(oxide)
Drain
(Collector)
PMOS
NMOS is similar
(swap P and N)
Background: Electron Bands
 Electrons in an atom can hold only certain energy levels
(allowed levels, quantized energy levels)
 Solution of Schroedinger’s equation
 When two identical atoms come close (eg. Silicon and silicon),
electron levels split
 Pauli’s exclusion principle for fermions
 almost always valid (*neutron stars, black holes)
 When many atoms come together, allowed energy levels form
“bands”
 Electrons temporal/spatial position given by wave function
(uncertainity principle)
Background: Bands
1 Atom
Allowed
Energy
Levels
N Atom
Allowed
Energy
Levels
 When many atoms come together, the energy bands form
Background: Bands
 Energy bands and gaps depend on space between the atoms
Energy
Space between atoms
Background: Solid groups
 Solids:
 Ionic bond, covalent bond, metallic bond
 insulator, metal, semiconductor
 Resistivity
 insulator: > 1Mohm-cm
 conductor: < 10 uohm-cm
 at room temperature
Background: Band gap
 Energy bands and gaps depend on space between the atoms
METAL
INSULATOR
Filled levels
Empty levels
Energy
BAND GAP
Space between atoms
Space between atoms
Background: Bandgap
 Semi conductors similar to insulators with small band gap (
1eV) (Insulators > 3eV)
 Valence band : Top most occupied band
 Conduction band: lowest empty band
 Valence and conduction bands overlap: Metal
 Band gap: DE between top of valence band and bottom of
conduction band
 Metals: Band overlap
Background: Resistance vs Temp
 Indirect and Direct Band Gap
 Silicon - indirect, GaAs- Direct band gap
 phonon assisted jump (momentum, energy)
 Resistance vs Temp
 phonon scattering: metal:
 electron in conduction bands/ holes in valence bands:
semiconductor
Background: Semiconductors
 Silicon is “intrinsic” semiconductor
 Addition of other ‘contaminant’ (Dopant) to alter its
conductivity : Extrinsic
 N Type (negative) or P Type (positive)
 Donor electron, Acceptor hole (larger effective
mass)
 Phosphorous for N Type, Boron for P Type (for

Overall neutrality is maintained (number
IIIA
IVA
VA
VIA
example)
5
6
7
8
of protons = number of electrons)
B C N O
13
 Counter doping (when some P and some
N type materials are added)
 (junction is where N = P)
Al
14
Si
31
15
P
32
16
S
33
34
Ga Ge As Se
49
In
50
51
Sn Sb Te
52
Background: Conduction
 For intrinsic semiconductors (based on calculations)
   EC  EF  
n  N c exp 

kT


   EF  EV  
p  NV exp 

kT


 EF - Fermi level. Energy where the prob(electron) = 0.5
 = half way between EC and EV for semiconductor
Eg

   EC  EV  
kT
np  N c NV exp 
  NC NV e
kT


 For intrinsic case, n = p
Background: Doping
N Atom
Allowed
Energy
Levels
Conduction
N Doping
P Doping
EF
Valence
 Doping shifts Fermi level, smaller “band gap”
 Extrinsic Semiconductor : “n” not equal to “p”
Dopant Valence Band
Background: Doping
 Majority carrier, Minority carrier
 Carrier Mobility
 hole has heavier (effective) mass
 less mobile
 P-N junction
 depletion region
PN junction
EC
EF
EV
N Type
P Type
EF
EF
N
P
Background: Bias
 Reverse Bias and Forward Bias
 N connected with -ve, P with +ve : Forward Bias
 Opposite polarity : Reverse Bias
 increase in depletion region
I-V curve
I
Reverse
Forward
MOS CAPACITOR
N
Oxide +- +- +- +P
+
Accumulation
+
+ + N+ +
- - - P
Depletion
+
+ + N+ +
- - - P
-
Inversion
Mobile electrons
at the oxide
Oxide
+
depletion
Simple Capacitor
interface.
two capacitors in series
Immobile -ve ions in the solid
 Similar results if the ‘top’ N is replaced by metal
 Originally metal was used
 Metal-Oxide-Semiconductor structure or MOS structure
MOS FET
 Transistor using Electric Field to control
 Field Effect Transistor or FET
 Made with MOS ==> MOSFET
 Other types: JFET (Junction FET), MESFET etc
Drain
(Collector)
N-MOSFET (NMOS in short)
Gate (Base)
+
-
N+
N+
P
N+
Source
(Emitter)
MOS FET: Structure
 NMOS: By definition, Source is at lower voltage than drain
 PMOS: By definition, Source is at higher voltage than drain
 NMOS: IDS (Drain to Source current) is positive
 PMOS: IDS is negative
NMOS
Drain
(Collector)
Gate (Base)
+
-
N+
N+
P
N+
Source
(Emitter)
NMOS: Operation
 Negative gate voltage:
 Accumulation of holes in P region, near oxide
 No formation of Channel
NMOS
Drain
(Collector)
Gate (Base)
+
N+
- -N+
-++++
P
N+
Source
(Emitter)
NMOS: Operation
 Positive gate voltage:
 Depletion of holes near the oxide
 No channel formation
NMOS
Drain
(Collector)
Gate (Base)
+
N+
N+
+
P
N+
Source
(Emitter)
NMOS: Operation
 MORE positive gate voltage
 Inversion: Accumulation of electrons in P region (minority
carrier is more than the majority carrier) near oxide
 Formation of Channel
NMOS
Drain
(Collector)
Gate (Base)
+
N+
N+
++++
---P
 Trapped charges in gate ==> Flash memory
N+
Source
(Emitter)
NMOS: Operation
 Threshold Voltage VT, Gate Voltage VG , Source Voltage VS
and Drain Voltage VD.
 If Source is grounded, then VDS is same as VD
NMOS inversion
Drain
(Collector)
Gate (Base)
+
N+
N+
++++
---P
N+
Source
(Emitter)
NFET Behavior
 For VG > VT , Channel forms
 (VG - VT ) is the overdrive
 Small shifts in VG causes large changes in IDS
 VT depends on Doping in P and oxide thickness
 IDS depends on VG and VDS
 Analogy: Water flow (from MIT EE web site)
 Source and Drains are two tanks, Channel is pipe connecting
two tanks and Gate is the valve
 VDS is the height difference between source and drain tanks
 VG indicates the position of valve
 Opening the valve more increases flow (electron
concentration)
 Increasing the height difference increases the flow (field)
NFET Behavior
 Beyond a limit, increase in height VDS changes the behavior
 No more increase in current flow (for a given VG)
NFET I-V curve
When VDS is very large (> VG-VT)
VG-VT=0.6 V
LINEAR
IDS
Saturation current
SATURATION
VG-VT=0.4 V
IDS
VG - VT = 0.2V
VT
VG = VT
VG
V
CUT OFF DS
IDSAT depends on VG and on the gate length (channel length)
NMOS: Operation
NMOS
Drain
(Collector)
Gate (Base)
+
N+
N+
++++
---P
-
Source
(Emitter)
N+
 NOTE: Inversion layer will be thicker near source and thinner
near drain
NMOS: Pinch Off
NMOS
Drain
(Collector)
Gate (Base)
+
N+
N+
++++
---P
-
Source
(Emitter)
N+
 When VDS is very high (= VG-VT), Inversion layer thickness
becomes zero near drain
 Pinch off
 However, no barrier to current flow
NMOS: Beyond Pinch Off
NMOS
Drain
(Collector)
Gate (Base)
+
N+
N+
++++
---P
-
Source
(Emitter)
N+
 Beyond pinch off, increasing VDS does not cause increase in ID
 However, channel length becomes shorter and there is slight
increase in ID
MOSFET: Some issues
 Above conclusions based on VS=0 (grounded)
 Otherwise, VG refers to VGS
 When the field is high, electrons have high energy
 can damage the silicon/ oxide (gate) interface near drain
 Hot Carrier Effect
Gate (Base)
Drain
Source
(Collector) +
- (Emitter)
N+
++++
---N+
N+
P
 Reduce the doping concentration near Drain
 Lightly Doped Drain (LDD)
MOSFET: Some issues
 When channel is very short (gate length is short), depletion
regions in source and drain may merge
 short channel effect
 increase doping to keep VT non zero
 Refer to Device books for details of the above and other issues
MOSFET: Speed
 The time it takes to switch a transistor ON / OFF decides the
speed of a digital circuit
 shorter Gate length ==> Faster switching ON/OFF
Drain
(Collector)
Gate (Base)
+
N+
N+
++++
----
P
N+
Source
(Emitter)
MOSFET: Device
 If the base is also lightly doped N, it is depletion mode device
(ON by default). Current schematic is Enhancement mode device
(OFF by default). Most devices are Enhancement mode devices
 Depletion devices in imperfect crystals (historical)
Drain
(Collector)
Gate (Base)
+
N+
N+
++++
----
P
N+
Source
(Emitter)
FEOL: MOSFET
 Combination of PMOS and NMOS is called “Complementary
MOS” or CMOS
 When a voltage is applied to the gates, one transistor is on and
the other is off
CMOS - Advantages
 Scalable
 Power consumption is low
 Any any point of time, one of the devices
is “off”