Transcript The source drivers for the portable small-scale TFT-LCD

Strained-Si Devices and Circuits
for Low-Power Applications
系所:積體電路研究所
指導教授:易序忠 教授
學號:95662005
姓名:李俊志
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Outline
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Introduction
Strained-S i Device Features
Strained-S i CMOS inverter
Strained-S i CMOS circuits
Result and Discussion
Conclusion
References
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Introduction
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higher carrier mobility with preservation of conventional
CMOS device structure and geometry, strained-Si (SS)
MOSFETs are recently of much interest for highperformance
circuit applications
Due to the speed advantage, SS devices could be applied to
low-power circuit by lowering supply voltage, one of the
most effective ways for low-power circuit design.
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Strained-Si Device Features
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Based on the same technology node, strained-S i
CMOS has the advantages of mobility enhancement to
overcome the issues of mobility degradation due to
scaling down.. To breakthrough the bottlenecks of the
strained-S i CMOS technology - high quality S I G e
virtual substrate formation and device structure
design/integration including global and local strain, the
platform of high performance CMOS process/device
with mobility enhancement will be developed for the
high-end S o C product.
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技術規格:S i G e Virtual Substrate – thickness
< 1.0um, threading dislocation density <
104~5/cm2 Carrier mobility enhancement –
electron > 70%, hole > 60%
技術特寫:高品質矽鍺虛擬基材的形成技術全面
與局部形變的元件結構設計及製程整合技術
競爭力：相容性佳：與CMOS製程相容
突破點：崁入Si、SiC中間層之SiGe虛擬基材形
成技術，有效降低其厚度
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Strained-Si CMOS Inverter
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Strained-S i CMOS Inverter
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The bulk-SS inverter is significantly fast
VDD could be reduced by 85mv for the
SS CMOS, which would decrease the
static (DC) and (AC) power
consumptions.
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圖一 Predicted delays per stage of unloaded 9-stageinverter ring oscillator
for bulk-S i and bulk-SS devices
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For equal delay =15ps , DC power is
~20% lower in the SS device than the
bulk-S i counterpart , Note that for
equal VDD,DC power is comparable
since V t is made equal, The lower VDD
would yield less DIBL, thereby reducing
I off and DC power.
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圖二 Predicted normalized static (DC) and dynamic (AC) power
consumptions of the unloaded ring oscillator for bulk-S i and bulk-SS
device in equal delay
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Strained-Si CMOS Circuits
圖三 Static 4-way NAND circuit with bulk-S i and bulk-SS device :dynamic
power versus frequency and static power for
(A.B.C.D)=(1.1.1.1),(1,1,1,0),(1,1,0,0),(1,0,0,0),(0,0,0,0)
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Result and Discussion
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DIBL:長通道元件閘極下方的空乏區電荷
沿著源極到汲極呈現常數值的狀態分佈,
當汲極電壓增加時,並不會影響其能帶的
分佈狀態.
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圖四 SI-SIO2接面能帶圖
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圖五 DIBL效應對輸出電阻的影響
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Conclusions
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References
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