Transcript Ans: well implantation, field implantation, field

Homework: CMOS Fabrication
Digital IC Design : Martin Page 62
• 2.1 Discuss briefly the relationships between an ion beam’s
acceleration potential, the beam current, and the time of implantation
on the resulting doping profile.
Ans: Acceleration potential determines depth of implantation;beam current
and exposure time determine dosage
• 2.2 Place the following processing steps in their correct order: metal
deposition and patterning, field implantation, junction implantation, well
implantation, polysilicon deposition and patterning, field-oxide growth.
Ans: well implantation, field implantation, field-oxide growth, polysilicon
deposition and patterning, junction implantation, metal deposition and
patterning
• 2.3 What are major problems associated with a single thresholdvoltage-adjust implant?
Ans: NWELL and psubstrate generally have different doping levels, may
be difficult to achieve required threshold voltages by a single
adjustment step: for optimal well doping adjust thresholds separately
Homework: CMOS Fabrication
Digital IC Design : Martin Page 62
•
2.4 What is the reason for using a field implant and why is it often not needed
in the well regions?
Ans: Implant guarantees that Si under FOX will never invert when large voltages
are in vicinity; better device isolation
• 2.5 What are the major trade-offs in using a wet process or a dry process when
growing thermal SiO2?
Ans: Wet process faster since water vapor diffuses in Si faster than oxygen gas
but lower quality porous oxide results. Dry process gives higher density oxide
• 2.6 Why is polysilicon used to realize gates of MOS transistors rather than
metal?
Ans: Poly gates (as opposed to metal) permit a self-aligned process, eliminating
need for another mask.Poly mask defines transistor channel area
2.7 Why can a microcircuit not be annealed after metal has been deposited?
Ans:Annealing is a high temp process, metal distribution may be adversely
affected
EE565 Fall 2000 Exam 1 Tues Oct 10, 4.15pm – 5.30pm UT 111
Answer ALL Questions
1(a) Write the general expression for MOSFET drain current as a function of gate-source and
drain-source voltages
(1 point)
(b) For NMOS with Cox =92A/v*2, W =6m and L=0.8m,
Vgs-Vth = 1volt, calculate drain current for Vds=0.5V.
(2points)
© What happens to Id for drain source voltages in excess of Vgs-Vth ?
(1 point)
2. For the CMOS logic inverter circuit of fig 1,
(a) sketch the transfer characteristics Vo versus Vin
(2 points)
(b) Identify 5 regions of operation based on NMOS and PMOS
regimes of operation
(3 points)
© Using the CMOS inverter for illustration, briefly discuss noise margins (4 points)
EE565 Fall 2000 Exam 1 Continued
3. (a) Why is the “self-aligned” MOS fabrication process so called?
( 1point)
(b) What is photolithography and what are design rules ?
(2 points)
What impact does photolithography have on the design rules?
(1 point)
© Compare and contrast 2 techniques commonly used to introduce
dopants (3 points)
(d) Make a chronological list of masks involved in the CMOS n-well
fabrication process and write a one sentence description of the role
of each. (6 points)
(e) Consider a chip design using 10 mask levels. Suppose each mask
can be made with 98% catastrophic yield, determine the composite
mask yield for the chip.
(2 points)
(f) Identify the following by writing names on inverter layout in figure
1:
(4 points)
(1) body plugs
(2) PMOS gate, NMOS source and PMOS drain
(3) circuit inputs and outputs
(4) metal-polysilicon contact
(5) active contacts
AAI/101000/EX1
Total Points =32
EE565 Fall 2K Final Exam Thur Dec 14, 2000
Answer ALL Questions
1. Explain the circuit partitioning problem for ASICs and comment on problem complexity (2 points)
Formulate partitioning problem as optimization problem
(1 point)
Describe one procedure which can be employed to locate the globally
optimal partition (limit ½ page).
(4 points)
2. With the aid of a diagram describe the structure and operation of a commonly occuring
three terminal device in Gallium Arsenide technology (limit ½ page of narrative).
(3 points)
State 3 major advantages of GaAs technology over silicon and explain why dominance
over silicon is unlikely in the near future
(2 points)
Consider the Direct Coupled Logic gate of fig 1. Calculate approximate average power
dissipation assuming driver transistor widths of 8um and load transistor width of 3.5um
using the parameters supplied in the figure.
(3 points)
1. Differentiate between catastrophic and parametric yield with reference to mass
produced digital ASICs
(2 points)
What two groups of variables influence parametric yield and which of these would you as
an ASIC circuit designer manipulate to improve parametric yield?
(1 point)
A student explores the 2D space of transistor widths W1 and W2 in order to optimize
the parametric yield of her CMOS inverter cell (fig 2a, 2b) and obtains the yield estimates
indicated via Monte Carlo analysis. Suggest a reasonable search direction for yield
optimization and indicate an upper bound on step size in the selected direction.
Hence suggest a set of transistor widths which would improve yield.
Give reasons for your answer.
(4 points)
4. Discuss the role of input pads in the protection of CMOS ASICs.
(3 points)
What are the sources of static and dynamic power dissipation in CMOS ASICs ?
(3 points)
Compute dynamic power dissipation for a 16-bit CMOS stack operated at a frequency
of 10MHz from a 3V power rail if the loading capacitance is a 16bit register having
an input capacitance of 20pF
(2 points)
AAI/121400/HREX3
Total Points = 30
EE565 Digital VLSI
Design Exam2
Nov 21 2000
Answer ALL Questions (a one-sheet summary of course information is permitted)
1. (a) A store register has one express and 3 regular ones. It is store policy that the
express register be open when 2 or more of the other registers are busy.
Assume that Boolean variables A, B, C reflect the status of each of the regular
registers (1=busy, 0=idle). Design a logic circuit in CMOS with A, B, C as
inputs and F as output to automatically notify the manager by setting F=1 to
open the express register.
(4 points)
(b) Compare and contrast pseudo NMOS and CMOS logic.
(2 points)
Realize F in pseudo-NMOS logic.
(2 points)
2.(a) Write logic equations for a 1-bit adder with inputs A, B, carry-in Ck-1, carry-out Ck
and Sum S.
(2 points)
(b) Draw and describe briefly the operation of the switch-based implementation of the
one-bit adder
(5 points)
© Explain why this implementation is preferred to the gate-based in VLSI
implementation
(1 point)
(d) How can the adder be re-configured to implement the XOR function? (2 points)
3. (a) Define sheet resistance and standard gate capacitance
(2 points)
(b) Compute rise and fall times and sketch output pulse waveforms for the 3m wide
NWELL serpentine resistor (fig 1) given that NWELL sheet resistance is 2K/sq
and NWELL /p-substrate capacitance is 60aF/sq m.
(4 points)
4. (a) Describe briefly the operation of a 3-transistor dynamic RAM cell. (5 points)
(b) How is this circuit made more area efficient in today’s high density
memories?
(1 point)
Fig 1
Double Click on Image to see a clearer picture
Double Click on Image to see a clearer picture