Transcript Impact on CMOS imagers

Fabrication of CMOS Imagers
Vinay Keswani
Graduate Student
Imaging Science Department
02/19/04
Outline
• Introduction
• Impact on CMOS imagers
• Feature Size
• Impact of VDD
• Substrate Doping
• Oxide Thickness
• Conclusion
• References
Introduction

The first part of the idea of using
“standard”CMOS technology for imagers is to
use a widespread accessible process
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With well-developed design tools
Standard design libraries
Fast turn-around time
Introduction
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However, the question was naturally asked
about how the rapid development of
these“standard” processes would influence the
imager performance.
Each aspect of scaling will be considered
individually, along with the potential impact on
CMOS imagers.
Feature Size

A new generation of CMOS devices is
developed every three years, or less
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Device dimensions are less than 0.7 times those of
the previous generation
0.13 µm technology is in production
This is driven by the desire for
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Lower power consumption
Higher speeds and Improved fill factor
Increased functionality and number of transistors
Feature size trend
Lower VDD

Partly forced by reduced dimensions
 Because electric fields cannot be too high
(Electric Field = - VDD / X)
e.g. hot carrier effects & tunneling
Lower VDD 1V
Impact on CMOS imagers
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Reduced analog voltage swing, VDD – VT
Reduced dynamic range
Analog signal processing becomes difficult
Substrate Doping

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Xj (Junction Depth) - Source,Drain are
dependent on the substrate doping of the wafer
(Xj ~ 1/ Nsub)
Substrate doping is increasing over the years in
order to minimize short-channel effects
e.g. Punchthrough
Substrate Doping
Impact on CMOS imagers

Due to associated reduction in minority carrier
diffusion length, Ln

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Good – reduces crosstalk between pixels
Bad – reduces effective volume for photo-charge
collection.
Oxide Thickness
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As the supply voltage decreases, so too must
the threshold voltage
Although this is also affected by substrate
doping
VT is dependent on 1/Cox, and therefore tox
must be reduced, since Cox = eSi/tox
Oxide Thickness
Impact on CMOS imagers

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Reduced voltage swing, as before, since VDD
scales
Gate tunneling current potentially important for
some MOS capacitor devices
Conclusion
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In the end, the balance depends on the
application
It is likely that a continuum of techniques will
develop between pure CCD and pure CMOS or
the combination of both….
References
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Silicon VLSI Technology by Plummer
P. Lee et al. (1995), “An active pixel sensor
fabricated using CMOS/CCD process
technology”, 1995 IEEE Workshop on CCDs
and Advanced Image Sensors, Dana Point, CA
Acknowledgements

Thank you very much to Prof. Rolando for his
support and help !!!
Questions