Transcript Dynamic Gate

Dynamic CMOS
Chapter 9 of Textbook
1
Dynamic CMOS

In static circuits at every point in time (except when
switching) the output is connected to either GND or VDD
via a low resistance path.


fan-in of N requires 2N devices
Dynamic circuits rely on the temporary storage of signal
values on the capacitance of high impedance nodes.


requires only N + 2 transistors
takes a sequence of precharge and conditional evaluation
phases to realize logic functions
2
Dynamic Gate
CLK
CLK
Mp
off
Mp on
Out
In1
In2
In3
CLK
CL
PDN
1
Out
!((A&B)|C)
A
C
B
Me
CLK
off
Me on
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
4
Conditions on Output

Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.

Inputs to the gate can make at most one transition during
evaluation.

Output can be in the high impedance state during and
after evaluation (PDN off), state is stored on CL
5
Properties of Dynamic Gates

Logic function is implemented by the PDN only


number of transistors is N + 2 (versus 2N for static
complementary CMOS)
should be smaller in area than static complementary CMOS

Full swing outputs (VOL = GND and VOH = VDD)

Nonratioed - sizing of the devices is not important for
proper functioning (only for performance)

Faster switching speeds




reduced load capacitance due to lower number of transistors per
gate (Cint) so a reduced logical effort
reduced load capacitance due to smaller fan-out (Cext)
no Isc, so all the current provided by PDN goes into discharging CL
Ignoring the influence of precharge time on the switching speed of
the gate, tpLH = 0 but the presence of the evaluation transistor
slows down the tpHL
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Properties of Dynamic Gates, con’t

Power dissipation should be better





But power dissipation can be significantly higher due to

higher transition probabilities

extra load on CLK
PDN starts to work as soon as the input signals exceed
VTn, so set VM (switching threshold), VIH and VIL all equal to VTn


consumes only dynamic power – no short circuit power
consumption since the pull-up path is not on when evaluating
lower CL- both Cint (since there are fewer transistors connected to
the drain output) and Cext (since there the output load is one per
connected gate, not two)
by construction can have at most one transition per cycle – no
glitching
low noise margin (NML= VIL – VoL)
Needs a precharge clock
7
Dynamic Behavior
CLK
2.5
Out
Evaluate
1 In1
1 In2
1.5
1 In3
In &
CLK
0.5
1 In4
CLK
Out
Precharge
-0.5
0
0.5
#Trns
VOH
VOL
VM
NMH
6
2.5V
0V
VTn 2.5-VTn
Time, ns
NML
VTn
tpHL
1
tpLH
tpre
110ps 0ns 83ps
8
Gate Parameters are Time Independent
The amount by which the output voltage drops is a
strong function of the input voltage and the available
evaluation time.

Noise needed to corrupt the signal has to be larger if the
evaluation time is short – i.e., the switching threshold is truly
time independent.
CLK
2.5
Voltage (V)

Vout (VG=0.45)
VG is the input
glitch
1.5
Vout (VG=0.55)
Vout (VG=0.5)
0.5
-0.5
0
20
40
60
Time (ns)
80
100
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Power Consumption of Dynamic Gate
CLK
Mp
Out
In1
In2
In3
CLK
CL
PDN
Me
Power only dissipated when previous Out = 0
10
Dynamic Power Consumption is Data Dependent
Dynamic 2-input NOR Gate
A
B
Out
0
0
1
0
1
0
1
0
0
1
1
0
Assume signal probabilities
PA=1 = 1/2
Out
PB=1 = 1/2
precharge
to 1, so Pout=1 =1
Then transition probability
P01 = Pout=0 x Pout=1
= 3/4 x 1 = 3/4
Switching activity can be higher in dynamic gates!
P01 = Pout=0=3/4
static NOR gate P01 = 3/16 = Pout=0 x Pout=1=3/4 x ¼ = 3/16
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Issues in Dynamic Design 1: Charge Leakage
subthreshold conduction
reverse bias diode
CLK
4
CLK
3
Mp
Out
1
CL
A=0
2
CLK
Evaluate
VOut
Me
Precharge
Leakage sources
Minimum clock rate of a few kHz
12
Impact of Charge Leakage
Output settles to an intermediate voltage determined by
a resistive divider of the pull-up and pull-down networks

Once the output drops below the switching threshold of the
fan-out logic gate, the output is interpreted as a low voltage.
CLK
2.5
Voltage (V)

Out
1.5
0.5
-0.5
0
20
Time (ms)
40
13
A Solution to Charge Leakage

Keeper compensates for the charge lost due to the pulldown leakage paths.
Keeper
CLK
Mp
Mkp
!Out
A
CL
B
CLK
Me
Figure 9.33 on page 387
Same approach as level restorer for pass
transistor logic
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Issues in Dynamic Design 2: Charge Sharing
CLK
Mp
Out
A
CL
B=0
CLK
Ca
Me
Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
static power consumption by
downstream gates and
possible circuit malfunction.
Cb
When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is
large enough to be below the switching threshold of
the gate it drives causing a malfunction.
15
Charge Sharing Example
What is the worst case voltage drop on y? (Assume all inputs are low
during precharge and that all internal nodes are initially at 0V.)
CLK
a
Ca=15fF
B
Cc=15fF
c
A
y=ABC
!A
Load
inverter
Cy=50fF
b
!B
B
!C
C
!B
d
Cb=15fF
Cd=15fF
CLK
.
Vout = - VDD ((Ca + Cc)/((Ca + Cc) + Cy))
= - 2.5V*(30/(30+50)) = -0.94V
Load inverter should have
switching threshold below
2.5 – 0.94 = 1.56V
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Solution to Charge Redistribution
CLK
Mp
Mkp
CLK
Out
A
B
CLK
Me
Precharge internal nodes using a clockdriven transistor (at the cost of increased
area and power)
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Issues in Dynamic Design 3: Backgate Coupling

Susceptible to crosstalk due to 1) high impedance of the
output node and 2) capacitive coupling

Out2 capacitively couples with Out1 through the gate-source and
gate-drain capacitances of M4
CLK
Mp
A=0
M1
B=0
M2
CLK
Out1 =1
CL1
M6
M5
Out2 =0
M4
CL2
M3
In
Me
Dynamic NAND
Static NAND
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Backgate Coupling Effect

Capacitive coupling means Out1 drops significantly so
Out2 doesn’t go all the way to ground
Due to clock feedthrough
3
2
Out1
1
CLK
0
Out2
In
-1
0
2
Time, ns
4
6
20
Issues in Dynamic Design 4: Clock Feedthrough

A special case of capacitive coupling between the clock
input of the precharge transistor and the dynamic output
node
CLK
Mp
A
CL
B
CLK
Out
Me
Coupling between Out and
CLK input of the precharge
device due to the gatedrain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.
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Clock Feedthrough
CLK
Clock feedthrough
Out
In1
2.5
In2
1.5
In3
In4
In &
CLK
0.5
Out
CLK
-0.5
0
0.5
Time, ns
1
Clock feedthrough
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Cascading Dynamic Gates
V
CLK
Mp
CLK
CLK
Mp
Out1
Out2
In
In
CLK
Me
CLK
Out1
Me
Out2
The second dynamic inverter turns
off (PDN) when Out1 reaches VTn
VTn
V
t
Only a single 0  1 transition allowed at the inputs during the evaluation period!
Out2 should remain at VDD since Out1 transitions to 0 during evaluation
a finite propagation delay for the input to discharge Out1 to GND, the
second output also starts to discharge. This loss will not be recovered
and may result in reduced noise margin and potential malfunction.
Setting all inputs to 0 during precharge
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Domino Logic
a static
inverter
CLK
In1
In2
In3
CLK
Mp
11
10
PDN
Me
Out1
a static
inverter
CLK
Mp Mkp
Out2
00
01
In4
In5
CLK
PDN
a static
inverter
Me
All inputs to the Domino gate are set to 0 at the end of the
precharge period. Hence, the only possible transition during
evaluation is 0 -> 1
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Why Domino?
CLK
In1
Ini PDN
Inj
CLK
Ini
Inj
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Like falling dominos!
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Domino Manchester Carry Chain
CLK
3
P0
3
4
Ci,0
CLK
P1
3
3
P2
3
2
P3
3
1
Ci,4
5 G0
4 G1
3 G2
2 G3
1
6
5
4
3
2
!(G0 + P0 Ci,0)
!(G1 + P1G0 + P1P0 Ci,0)
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Domino Comparator
CLK
A3
A2
A1
A0
Out
B3
B2
B1
B0
Out=1 if
unequal
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Properties of Domino Logic

Only non-inverting logic can be implemented, fixes
include



can reorganize the logic using Boolean transformations
use differential logic (dual rail)
use np-CMOS (zipper)
- Use nMOS logic gates and pMOS logic gates to perform
operation

Very high speed
 tpHL

=0
static inverter can be optimized to match fan-out (separation of
fan-in and fan-out capacitances)
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Differential (Dual Rail) Domino
off
CLK
Out = AB
1
on
Mp Mkp
Mkp
0
CLK
Mp
0 !Out = !(AB)
1
A
!A
!B
B
CLK
Me
Due to its high-performance, differential domino is
very popular and is used in several commercial
microprocessors!
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np-CMOS (Zipper)
CLK
In1
In2
In3
CLK
Mp
11
10
Out1
!CLK
In4
In5
PDN
Me
PUN
00
01
!CLK
Me
to other
PDN’s
Mp
Out2
(to PDN)
to other
PUN’s
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
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DCVS Logic
10
Out
In1
!In1
In2
!In2
on  off
PDN1
off  on
off  on
01
!Out
PDN2
on off
PDN1 and PDN2 are mutually exclusive
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DCVS Logic Example
!Out
Out
B
!B
xnor
A
!B
B
xor
!A
What is the logic ?
35
How to Choose a Logic Style

Must consider ease of design, robustness (noise immunity),
area, speed, power, system clocking requirements, fan-out,
functionality, ease of testing
4-input NAND
Style
# Trans
Comp Static
8
CPL*
12 + 2
domino
6+2
DCVSL*
10
Ease
1
2
4
3
Ratioed? Delay Power
no
3
1
no
4
3
no
2
2 + clk
yes
1
4
* Dual Rail

Current trend is towards an increased use of
complementary static CMOS: design support through DA
tools, robust, more amenable to voltage scaling.
CPL: Complemantary Pass-transistor Logic
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